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| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-11 18:34:12 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-11 18:34:12 +0000 |
| commit | e679d3331b5fb4747c5f03b546376f8fdb6a25d4 (patch) | |
| tree | ec10b87b7d8e289c572b11d05909bb28d07ebcc9 /test/MC | |
| parent | bd3327654b5708f1ba92aff3ab25b1bbf5034797 (diff) | |
| download | llvm-e679d3331b5fb4747c5f03b546376f8fdb6a25d4.tar.gz llvm-e679d3331b5fb4747c5f03b546376f8fdb6a25d4.tar.bz2 llvm-e679d3331b5fb4747c5f03b546376f8fdb6a25d4.tar.xz | |
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
invalid instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt | 10 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt | 4 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt | 10 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt | 10 |
4 files changed, 34 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt new file mode 100644 index 0000000000..7a35c2d6ce --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# if wback && (n == 15 || n == t) then UNPREDICTABLE +0x05 0x70 0xd7 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt new file mode 100644 index 0000000000..ad79986b25 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# LDR_PRE/POST has encoding Inst{4} = 0. +0xde 0x69 0x18 0x46 diff --git a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt new file mode 100644 index 0000000000..36c1124bce --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if m == 15 then UNPREDICTABLE +0x8f 0x60 0xb7 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt b/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt new file mode 100644 index 0000000000..5209323fa8 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if t == 15 then UNPREDICTABLE +0x00 0xf0 0xcf 0xe7 |