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| author | Daniel Dunbar <daniel@zuster.org> | 2009-08-11 02:59:53 +0000 |
|---|---|---|
| committer | Daniel Dunbar <daniel@zuster.org> | 2009-08-11 02:59:53 +0000 |
| commit | ea6408f8cd17b065e414611e01a7133d118429e9 (patch) | |
| tree | 0410cd4013d866f51f66521ccab7b800c69ab686 /test/MC | |
| parent | a418628d30dce6ef0f49a348e4a0ccb9eb8aea4f (diff) | |
| download | llvm-ea6408f8cd17b065e414611e01a7133d118429e9.tar.gz llvm-ea6408f8cd17b065e414611e01a7133d118429e9.tar.bz2 llvm-ea6408f8cd17b065e414611e01a7133d118429e9.tar.xz | |
llvm-mc/AsmParser: Implement automatic classification of RegisterClass operands.
- This drops us to 123 ambiguous instructions (previously ~500) on X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78636 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
| -rw-r--r-- | test/MC/AsmParser/x86_instructions.s | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/test/MC/AsmParser/x86_instructions.s b/test/MC/AsmParser/x86_instructions.s index 1ddd9e3b38..436e2e08fb 100644 --- a/test/MC/AsmParser/x86_instructions.s +++ b/test/MC/AsmParser/x86_instructions.s @@ -30,9 +30,22 @@ subl $256, %eax // FIXME: Check that this matches XOR64ri8 -// RUN: grep {MCInst(opcode=.*, operands=.reg:19, reg:0, val:1.)} %t - xorq $1, %eax +// RUN: grep {MCInst(opcode=.*, operands=.reg:80, reg:0, val:1.)} %t + xorq $1, %rax // FIXME: Check that this matches XOR64ri32 -// RUN: grep {MCInst(opcode=.*, operands=.reg:19, reg:0, val:256.)} %t - xorq $256, %eax +// RUN: grep {MCInst(opcode=.*, operands=.reg:80, reg:0, val:256.)} %t + xorq $256, %rax + +// FIXME: Check that this matches SUB8rr +// RUN: grep {MCInst(opcode=.*, operands=.reg:5, reg:0, reg:2.)} %t + subb %al, %bl + +// FIXME: Check that this matches SUB16rr +// RUN: grep {MCInst(opcode=.*, operands=.reg:8, reg:0, reg:3.)} %t + subw %ax, %bx + +// FIXME: Check that this matches SUB32rr +// RUN: grep {MCInst(opcode=.*, operands=.reg:21, reg:0, reg:19.)} %t + subl %eax, %ebx + |