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| author | Silviu Baranga <silviu.baranga@arm.com> | 2012-04-18 13:12:50 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-04-18 13:12:50 +0000 |
| commit | fa1ebc6abe95b79b7f82030eea53586a8704eb7e (patch) | |
| tree | 158b6ad7a4ddd16be07017fc6616a12f9bd8e53b /test/MC | |
| parent | e546c4c9c3004274c8e275e8303ca078b794bf28 (diff) | |
| download | llvm-fa1ebc6abe95b79b7f82030eea53586a8704eb7e.tar.gz llvm-fa1ebc6abe95b79b7f82030eea53586a8704eb7e.tar.bz2 llvm-fa1ebc6abe95b79b7f82030eea53586a8704eb7e.tar.xz | |
Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt | 4 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt | 13 |
2 files changed, 17 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt new file mode 100644 index 0000000000..aaae6ce2e4 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: invalid instruction encoding +0x00 0x1a 0x50 0xfc diff --git a/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt new file mode 100644 index 0000000000..26b286dbf4 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x00 0x10 0x51 0xfc +0x00 0x10 0x51 0xfc + +# CHECK: potentially undefined +# CHECK: 0x00 0xf0 0x41 0x0c +0x00 0xf0 0x41 0x0c + +# CHECK: potentially undefined +# CHECK: 0x00 0x00 0x4f 0x0c +0x00 0x00 0x4f 0x0c |