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| author | Owen Anderson <resistor@mac.com> | 2011-10-20 22:01:48 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-10-20 22:01:48 +0000 |
| commit | fe0748d696a69b66e11fce0256663070c0bb7e70 (patch) | |
| tree | d0ef8162a58865fb25941f9ffbccfb2f2e239131 /test/MC | |
| parent | e1d0b4fc252443299db87264aa4f3a889b7480aa (diff) | |
| download | llvm-fe0748d696a69b66e11fce0256663070c0bb7e70.tar.gz llvm-fe0748d696a69b66e11fce0256663070c0bb7e70.tar.bz2 llvm-fe0748d696a69b66e11fce0256663070c0bb7e70.tar.xz | |
Fix decoding tests for fixed MSR encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142624 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
| -rw-r--r-- | test/MC/Disassembler/ARM/arm-tests.txt | 6 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/basic-arm-instructions.txt | 54 |
2 files changed, 5 insertions, 55 deletions
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 69a094dd68..36627a3488 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -161,12 +161,6 @@ # CHECK: cpsie if, #10 0xca 0x00 0x0a 0xf1 -# CHECK: msr CPSR_fc, r0 -0x00 0xf0 0x29 0xe1 - -# CHECK: msrmi CPSR_c, #4043309056 -0xf1 0xf4 0x21 0x43 - # CHECK: rsbs r6, r7, r8 0x08 0x60 0x77 0xe0 diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index fc7eda537a..06aa8f756d 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -744,65 +744,21 @@ # MSR #------------------------------------------------------------------------------ -# CHECK: msr CPSR_fc, #5 -# CHECK: msr APSR_g, #5 -# CHECK: msr APSR_nzcvq, #5 -# CHECK: msr APSR_nzcvq, #5 -# CHECK: msr APSR_nzcvqg, #5 -# CHECK: msr CPSR_fc, #5 # CHECK: msr CPSR_c, #5 # CHECK: msr CPSR_x, #5 -# CHECK: msr CPSR_fc, #5 -# CHECK: msr CPSR_fc, #5 -# CHECK: msr CPSR_fsx, #5 -# CHECK: msr SPSR_fc, #5 -# CHECK: msr SPSR_fsxc, #5 -# CHECK: msr CPSR_fsxc, #5 - -0x05 0xf0 0x29 0xe3 +# CHECK: msr CPSR_xc, #5 + 0x05 0xf0 0x24 0xe3 0x05 0xf0 0x28 0xe3 -0x05 0xf0 0x28 0xe3 0x05 0xf0 0x2c 0xe3 -0x05 0xf0 0x29 0xe3 -0x05 0xf0 0x21 0xe3 -0x05 0xf0 0x22 0xe3 -0x05 0xf0 0x29 0xe3 -0x05 0xf0 0x29 0xe3 -0x05 0xf0 0x2e 0xe3 -0x05 0xf0 0x69 0xe3 -0x05 0xf0 0x6f 0xe3 -0x05 0xf0 0x2f 0xe3 - -# CHECK: msr CPSR_fc, r0 -# CHECK: msr APSR_g, r0 -# CHECK: msr APSR_nzcvq, r0 -# CHECK: msr APSR_nzcvq, r0 -# CHECK: msr APSR_nzcvqg, r0 -# CHECK: msr CPSR_fc, r0 + # CHECK: msr CPSR_c, r0 # CHECK: msr CPSR_x, r0 -# CHECK: msr CPSR_fc, r0 -# CHECK: msr CPSR_fc, r0 -# CHECK: msr CPSR_fsx, r0 -# CHECK: msr SPSR_fc, r0 -# CHECK: msr SPSR_fsxc, r0 -# CHECK: msr CPSR_fsxc, r0 - -0x00 0xf0 0x29 0xe1 +# CHECK: msr CPSR_xc, r0 + 0x00 0xf0 0x24 0xe1 0x00 0xf0 0x28 0xe1 -0x00 0xf0 0x28 0xe1 0x00 0xf0 0x2c 0xe1 -0x00 0xf0 0x29 0xe1 -0x00 0xf0 0x21 0xe1 -0x00 0xf0 0x22 0xe1 -0x00 0xf0 0x29 0xe1 -0x00 0xf0 0x29 0xe1 -0x00 0xf0 0x2e 0xe1 -0x00 0xf0 0x69 0xe1 -0x00 0xf0 0x6f 0xe1 -0x00 0xf0 0x2f 0xe1 #------------------------------------------------------------------------------ # MUL |