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| author | Chris Lattner <sabre@nondot.org> | 2011-04-15 05:18:47 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2011-04-15 05:18:47 +0000 |
| commit | 7a2bdde0a0eebcd2125055e0eacaca040f0b766c (patch) | |
| tree | 1cd5fa470f290368855c9081cb213ed118812805 /test/TableGen | |
| parent | bcb8c6d09ee426e0f774e3412912f6ae9e5f78dd (diff) | |
| download | llvm-7a2bdde0a0eebcd2125055e0eacaca040f0b766c.tar.gz llvm-7a2bdde0a0eebcd2125055e0eacaca040f0b766c.tar.bz2 llvm-7a2bdde0a0eebcd2125055e0eacaca040f0b766c.tar.xz | |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/TableGen')
| -rw-r--r-- | test/TableGen/TargetInstrInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/TableGen/TargetInstrInfo.td b/test/TableGen/TargetInstrInfo.td index 146ef6fd76..6c39d5ce57 100644 --- a/test/TableGen/TargetInstrInfo.td +++ b/test/TableGen/TargetInstrInfo.td @@ -110,7 +110,7 @@ def SHL32rCL : Inst<(ops R32:$dst, R32:$src), [(set R32:$dst, (shl R32:$src, CL))]>; // The RTL list is a list, allowing complex instructions to be defined easily. -// Temporary 'internal' registers can be used to break instructions appart. +// Temporary 'internal' registers can be used to break instructions apart. let isTwoAddress = 1 in def XOR32mi : Inst<(ops addr:$addr, imm32:$imm), "xor $dst, $src2", 0x81, MRM6m, |