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authorJim Grosbach <grosbach@apple.com>2013-08-16 00:15:20 +0000
committerJim Grosbach <grosbach@apple.com>2013-08-16 00:15:20 +0000
commit4658ce9c1f023ca8198add9eabc9ec466d23c8cb (patch)
tree26c37ce3be02aae294fa95469a2dc3edc84318a1 /test/Transforms/InstCombine
parentda44b4f68bcf2adcb74214670a266b43a1a6888f (diff)
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InstCombine: Simplify if(x!=0 && x!=-1).
When both constants are positive or both constants are negative, InstCombine already simplifies comparisons like this, but when it's exactly zero and -1, the operand sorting ends up reversed and the pattern fails to match. Handle that special case. Follow up for rdar://14689217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188512 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms/InstCombine')
-rw-r--r--test/Transforms/InstCombine/and2.ll12
1 files changed, 12 insertions, 0 deletions
diff --git a/test/Transforms/InstCombine/and2.ll b/test/Transforms/InstCombine/and2.ll
index 504391aa48..e88fd59830 100644
--- a/test/Transforms/InstCombine/and2.ll
+++ b/test/Transforms/InstCombine/and2.ll
@@ -42,3 +42,15 @@ define <4 x i32> @test5(<4 x i32> %A) {
%2 = and <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %1
ret <4 x i32> %2
}
+
+; Check that we combine "if x!=0 && x!=-1" into "if x+1u>1"
+define i32 @test6(i64 %x) nounwind {
+; CHECK: @test6
+; CHECK-NEXT: add i64 %x, 1
+; CHECK-NEXT: icmp ugt i64 %x.off, 1
+ %cmp1 = icmp ne i64 %x, -1
+ %not.cmp = icmp ne i64 %x, 0
+ %.cmp1 = and i1 %cmp1, %not.cmp
+ %land.ext = zext i1 %.cmp1 to i32
+ ret i32 %land.ext
+}