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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-03-28 19:27:24 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-03-28 19:27:24 +0000 |
| commit | 53774a821d21f954c1ba0eaa493d4142b68fbfcd (patch) | |
| tree | 3810e8032fd5a4b43494860277c88a973bc4a8ca /test/Transforms/InstCombine | |
| parent | efdd4673d6e78f3d406c5d1f44316aef8a5a9a48 (diff) | |
| download | llvm-53774a821d21f954c1ba0eaa493d4142b68fbfcd.tar.gz llvm-53774a821d21f954c1ba0eaa493d4142b68fbfcd.tar.bz2 llvm-53774a821d21f954c1ba0eaa493d4142b68fbfcd.tar.xz | |
Use direct types in most PowerPC Altivec instructions and patterns.
This follows up Ulrich Weigand's work in PPCInstrInfo.td and
PPCInstr64Bit.td by doing the corresponding work for most of the
Altivec patterns. I have not been able to do anything for the
following classes of instructions:
(1) Vector logicals. These don't have corresponding intrinsics and
don't have a single obvious vector type. So far as I can tell I need
to leave these as VRRC. Affected instructions are: VAND, VANDC,
VNOR, VOR, VXOR, V_SET0.
(2) Instructions that make use of vector shuffle. The selection code
promotes all shuffles to v16i8, so any pattern that matches on a
shuffle is constrained. I haven't found any way to make the patterns
match on their natural types, so I plan to leave these as VRRC.
Affected instructions are: VMRG*, VSPLTB, VSPLTH, VSPLTW, VPKUHUM,
VPKUWUM.
No change in behavior is anticipated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178277 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms/InstCombine')
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