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| author | David Majnemer <david.majnemer@gmail.com> | 2013-07-30 21:01:36 +0000 |
|---|---|---|
| committer | David Majnemer <david.majnemer@gmail.com> | 2013-07-30 21:01:36 +0000 |
| commit | 36850ad779cb77930ab9e03bc1bde4ad47dc9dce (patch) | |
| tree | 55320cf98b59089420c34256837aa112a489eb72 /test/Transforms | |
| parent | f34dc428fa577d6d5d71ab3a1f9765b4e5da5a4f (diff) | |
| download | llvm-36850ad779cb77930ab9e03bc1bde4ad47dc9dce.tar.gz llvm-36850ad779cb77930ab9e03bc1bde4ad47dc9dce.tar.bz2 llvm-36850ad779cb77930ab9e03bc1bde4ad47dc9dce.tar.xz | |
isKnownToBeAPowerOfTwo: Strengthen isKnownToBeAPowerOfTwo's analysis on add instructions
Call into ComputeMaskedBits to figure out which bits are set on both add
operands and determine if the value is a power-of-two-or-zero or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187445 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms')
| -rw-r--r-- | test/Transforms/InstCombine/rem.ll | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/test/Transforms/InstCombine/rem.ll b/test/Transforms/InstCombine/rem.ll index 9272f83b12..22fd90bf7a 100644 --- a/test/Transforms/InstCombine/rem.ll +++ b/test/Transforms/InstCombine/rem.ll @@ -172,3 +172,35 @@ define i32 @test17(i32 %X) { %A = urem i32 1, %X ret i32 %A } + +define i32 @test18(i16 %x, i32 %y) { +; CHECK: @test18 +; CHECK-NEXT: [[AND:%.*]] = and i16 %x, 4 +; CHECK-NEXT: [[EXT:%.*]] = zext i16 [[AND]] to i32 +; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw i32 [[EXT]], 3 +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[SHL]], 63 +; CHECK-NEXT: [[REM:%.*]] = and i32 [[XOR]], %y +; CHECK-NEXT: ret i32 [[REM]] + %1 = and i16 %x, 4 + %2 = icmp ne i16 %1, 0 + %3 = select i1 %2, i32 32, i32 64 + %4 = urem i32 %y, %3 + ret i32 %4 +} + +define i32 @test19(i32 %x, i32 %y) { +; CHECK: @test19 +; CHECK-NEXT: [[SHL1:%.*]] = shl i32 1, %x +; CHECK-NEXT: [[SHL2:%.*]] = shl i32 1, %y +; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL1]], [[SHL2]] +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[AND]], [[SHL1]] +; CHECK-NEXT: [[SUB:%.*]] = add i32 [[ADD]], -1 +; CHECK-NEXT: [[REM:%.*]] = and i32 [[SUB]], %y +; CHECK-NEXT: ret i32 [[REM]] + %A = shl i32 1, %x + %B = shl i32 1, %y + %C = and i32 %A, %B + %D = add i32 %C, %A + %E = urem i32 %y, %D + ret i32 %E +} |