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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-04-14 21:50:37 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-04-14 21:50:37 +0000 |
commit | 448a1a07348dad12592cce2fe4d9413024b81308 (patch) | |
tree | cc8b377ffa13e0453e2e181a7157c7b4135a8e06 /test/Transforms | |
parent | 05620e5439d73e5ae43092d353bcb2c6a50d7eca (diff) | |
download | llvm-448a1a07348dad12592cce2fe4d9413024b81308.tar.gz llvm-448a1a07348dad12592cce2fe4d9413024b81308.tar.bz2 llvm-448a1a07348dad12592cce2fe4d9413024b81308.tar.xz |
Revert "Revert r206045, "Fix shift by constants for vector.""
Fix cases where the Value itself is used, and not the constant value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206214 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms')
-rw-r--r-- | test/Transforms/InstCombine/pr19420.ll | 67 | ||||
-rw-r--r-- | test/Transforms/InstCombine/shift.ll | 78 |
2 files changed, 145 insertions, 0 deletions
diff --git a/test/Transforms/InstCombine/pr19420.ll b/test/Transforms/InstCombine/pr19420.ll new file mode 100644 index 0000000000..23fa0a4097 --- /dev/null +++ b/test/Transforms/InstCombine/pr19420.ll @@ -0,0 +1,67 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +; CHECK-LABEL: @test_FoldShiftByConstant_CreateSHL +; CHECK: mul <4 x i32> %in, <i32 0, i32 -32, i32 0, i32 -32> +; CHECK-NEXT: ret +define <4 x i32> @test_FoldShiftByConstant_CreateSHL(<4 x i32> %in) { + %mul.i = mul <4 x i32> %in, <i32 0, i32 -1, i32 0, i32 -1> + %vshl_n = shl <4 x i32> %mul.i, <i32 5, i32 5, i32 5, i32 5> + ret <4 x i32> %vshl_n +} + +; CHECK-LABEL: @test_FoldShiftByConstant_CreateSHL2 +; CHECK: mul <8 x i16> %in, <i16 0, i16 -32, i16 0, i16 -32, i16 0, i16 -32, i16 0, i16 -32> +; CHECK-NEXT: ret +define <8 x i16> @test_FoldShiftByConstant_CreateSHL2(<8 x i16> %in) { + %mul.i = mul <8 x i16> %in, <i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1> + %vshl_n = shl <8 x i16> %mul.i, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> + ret <8 x i16> %vshl_n +} + +; CHECK-LABEL: @test_FoldShiftByConstant_CreateAnd +; CHECK: mul <16 x i8> %in0, <i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33> +; CHECK-NEXT: and <16 x i8> %vsra_n2, <i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32> +; CHECK-NEXT: ret +define <16 x i8> @test_FoldShiftByConstant_CreateAnd(<16 x i8> %in0) { + %vsra_n = ashr <16 x i8> %in0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> + %tmp = add <16 x i8> %in0, %vsra_n + %vshl_n = shl <16 x i8> %tmp, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> + ret <16 x i8> %vshl_n +} + + +define i32 @bar(i32 %x, i32 %y) { + %a = lshr i32 %x, 4 + %b = add i32 %a, %y + %c = shl i32 %b, 4 + ret i32 %c +} + +define <2 x i32> @bar_v2i32(<2 x i32> %x, <2 x i32> %y) { + %a = lshr <2 x i32> %x, <i32 5, i32 5> + %b = add <2 x i32> %a, %y + %c = shl <2 x i32> %b, <i32 5, i32 5> + ret <2 x i32> %c +} + + + + +define i32 @foo(i32 %x, i32 %y) { + %a = lshr i32 %x, 4 + %b = and i32 %a, 8 + %c = add i32 %b, %y + %d = shl i32 %c, 4 + ret i32 %d +} + +define <2 x i32> @foo_v2i32(<2 x i32> %x, <2 x i32> %y) { + %a = lshr <2 x i32> %x, <i32 4, i32 4> + %b = and <2 x i32> %a, <i32 8, i32 8> + %c = add <2 x i32> %b, %y + %d = shl <2 x i32> %c, <i32 4, i32 4> + ret <2 x i32> %d +} + + + diff --git a/test/Transforms/InstCombine/shift.ll b/test/Transforms/InstCombine/shift.ll index 8f0bbd1487..5586bb6527 100644 --- a/test/Transforms/InstCombine/shift.ll +++ b/test/Transforms/InstCombine/shift.ll @@ -40,6 +40,27 @@ define i32 @test5(i32 %A) { ret i32 %B } +define <4 x i32> @test5_splat_vector(<4 x i32> %A) { +; CHECK-LABEL: @test5_splat_vector( +; CHECK: ret <4 x i32> undef + %B = lshr <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out + ret <4 x i32> %B +} + +define <4 x i32> @test5_zero_vector(<4 x i32> %A) { +; CHECK-LABEL: @test5_zero_vector( +; CHECK-NEXT: ret <4 x i32> %A + %B = lshr <4 x i32> %A, zeroinitializer + ret <4 x i32> %B +} + +define <4 x i32> @test5_non_splat_vector(<4 x i32> %A) { +; CHECK-LABEL: @test5_non_splat_vector( +; CHECK-NOT: ret <4 x i32> undef + %B = shl <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> + ret <4 x i32> %B +} + define i32 @test5a(i32 %A) { ; CHECK-LABEL: @test5a( ; CHECK: ret i32 undef @@ -47,6 +68,20 @@ define i32 @test5a(i32 %A) { ret i32 %B } +define <4 x i32> @test5a_splat_vector(<4 x i32> %A) { +; CHECK-LABEL: @test5a_splat_vector( +; CHECK: ret <4 x i32> undef + %B = shl <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out + ret <4 x i32> %B +} + +define <4 x i32> @test5a_non_splat_vector(<4 x i32> %A) { +; CHECK-LABEL: @test5a_non_splat_vector( +; CHECK-NOT: ret <4 x i32> undef + %B = shl <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> + ret <4 x i32> %B +} + define i32 @test5b() { ; CHECK-LABEL: @test5b( ; CHECK: ret i32 -1 @@ -344,6 +379,20 @@ define i32 @test25(i32 %tmp.2, i32 %AA) { ret i32 %tmp.6 } +define <2 x i32> @test25_vector(<2 x i32> %tmp.2, <2 x i32> %AA) { +; CHECK-LABEL: @test25_vector( +; CHECK: %tmp.3 = lshr <2 x i32> %tmp.2, <i32 17, i32 17> +; CHECK-NEXT: shl <2 x i32> %tmp.3, <i32 17, i32 17> +; CHECK-NEXT: add <2 x i32> %tmp.51, %AA +; CHECK-NEXT: and <2 x i32> %x2, <i32 -131072, i32 -131072> +; CHECK-NEXT: ret <2 x i32> + %x = lshr <2 x i32> %AA, <i32 17, i32 17> + %tmp.3 = lshr <2 x i32> %tmp.2, <i32 17, i32 17> + %tmp.5 = add <2 x i32> %tmp.3, %x + %tmp.6 = shl <2 x i32> %tmp.5, <i32 17, i32 17> + ret <2 x i32> %tmp.6 +} + ;; handle casts between shifts. define i32 @test26(i32 %A) { ; CHECK-LABEL: @test26( @@ -780,3 +829,32 @@ bb11: ; preds = %bb8 bb12: ; preds = %bb11, %bb8, %bb ret void } + +define i32 @test64(i32 %a) { +; CHECK-LABEL: @test64( +; CHECK-NEXT: ret i32 undef + %b = ashr i32 %a, 32 ; shift all bits out + ret i32 %b +} + +define <4 x i32> @test64_splat_vector(<4 x i32> %a) { +; CHECK-LABEL: @test64_splat_vector +; CHECK-NEXT: ret <4 x i32> undef + %b = ashr <4 x i32> %a, <i32 32, i32 32, i32 32, i32 32> ; shift all bits out + ret <4 x i32> %b +} + +define <4 x i32> @test64_non_splat_vector(<4 x i32> %a) { +; CHECK-LABEL: @test64_non_splat_vector +; CHECK-NOT: ret <4 x i32> undef + %b = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2> ; shift all bits out + ret <4 x i32> %b +} + +define <2 x i65> @test_65(<2 x i64> %t) { +; CHECK-LABEL: @test_65 + %a = zext <2 x i64> %t to <2 x i65> + %sext = shl <2 x i65> %a, <i65 33, i65 33> + %b = ashr <2 x i65> %sext, <i65 33, i65 33> + ret <2 x i65> %b +} |