InstCombine: Modernize a bunch of cast combines.

Also make them vector-aware.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199608 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 57 insertions, 0 deletions

diff --git a/test/Transforms/InstCombine/vec_sext.ll b/test/Transforms/InstCombine/vec_sext.ll
index d7ab96b9cf..6f0d21476e 100644
--- a/test/Transforms/InstCombine/vec_sext.ll
+++ b/test/Transforms/InstCombine/vec_sext.ll
@@ -13,6 +13,7 @@ entry:
   %cond = or <4 x i32> %2, %3
   ret <4 x i32> %cond
 
+; CHECK-LABEL: @psignd_3
 ; CHECK:   ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
 ; CHECK:   sub nsw <4 x i32> zeroinitializer, %a
 ; CHECK:   xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -20,3 +21,25 @@ entry:
 ; CHECK:   and <4 x i32> %b.lobit, %sub
 ; CHECK:   or <4 x i32> %1, %2
 }
+
+define <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b) nounwind ssp {
+entry:
+  %cmp = icmp sgt <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %sub = sub nsw <4 x i32> zeroinitializer, %a
+  %0 = icmp slt <4 x i32> %sext, zeroinitializer
+  %sext3 = sext <4 x i1> %0 to <4 x i32>
+  %1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %2 = and <4 x i32> %a, %1
+  %3 = and <4 x i32> %sext3, %sub
+  %cond = or <4 x i32> %2, %3
+  ret <4 x i32> %cond
+
+; CHECK-LABEL: @test1
+; CHECK:   ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
+; CHECK:   xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
+; CHECK:   sub nsw <4 x i32> zeroinitializer, %a
+; CHECK:   and <4 x i32> %b.lobit, %a
+; CHECK:   and <4 x i32> %b.lobit.not, %sub
+; CHECK:   or <4 x i32> %0, %1
+}
diff --git a/test/Transforms/InstCombine/zext.ll b/test/Transforms/InstCombine/zext.ll
index 10eabf7aed..b62c626c95 100644
--- a/test/Transforms/InstCombine/zext.ll
+++ b/test/Transforms/InstCombine/zext.ll
@@ -5,7 +5,41 @@ define i64 @test_sext_zext(i16 %A) {
         %c1 = zext i16 %A to i32                ; <i32> [#uses=1]
         %c2 = sext i32 %c1 to i64               ; <i64> [#uses=1]
         ret i64 %c2
+
+; CHECK-LABEL: @test_sext_zext
 ; CHECK-NOT: %c1
 ; CHECK: %c2 = zext i16 %A to i64
 ; CHECK: ret i64 %c2
 }
+
+define <2 x i64> @test2(<2 x i1> %A) {
+  %xor = xor <2 x i1> %A, <i1 true, i1 true>
+  %zext = zext <2 x i1> %xor to <2 x i64>
+  ret <2 x i64> %zext
+
+; CHECK-LABEL: @test2
+; CHECK-NEXT: zext <2 x i1> %A to <2 x i64>
+; CHECK-NEXT: xor <2 x i64> %1, <i64 1, i64 1>
+}
+
+define <2 x i64> @test3(<2 x i64> %A) {
+  %trunc = trunc <2 x i64> %A to <2 x i32>
+  %and = and <2 x i32> %trunc, <i32 23, i32 42>
+  %zext = zext <2 x i32> %and to <2 x i64>
+  ret <2 x i64> %zext
+
+; CHECK-LABEL: @test3
+; CHECK-NEXT: and <2 x i64> %A, <i64 23, i64 42>
+}
+
+define <2 x i64> @test4(<2 x i64> %A) {
+  %trunc = trunc <2 x i64> %A to <2 x i32>
+  %and = and <2 x i32> %trunc, <i32 23, i32 42>
+  %xor = xor <2 x i32> %and, <i32 23, i32 42>
+  %zext = zext <2 x i32> %xor to <2 x i64>
+  ret <2 x i64> %zext
+
+; CHECK-LABEL: @test4
+; CHECK-NEXT: xor <2 x i64> %A, <i64 4294967295, i64 4294967295>
+; CHECK-NEXT: and <2 x i64> %1, <i64 23, i64 42>
+}