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| author | Owen Anderson <resistor@mac.com> | 2011-03-18 22:50:18 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-03-18 22:50:18 +0000 |
| commit | 0082830cb26248178fe5cc9bbdbd00881556c33d (patch) | |
| tree | b8dd68f295c4b9918579ebee6883fb67a4b88d21 /test | |
| parent | 31649e61bcead26a63c7cd452da90fff5e000b91 (diff) | |
| download | llvm-0082830cb26248178fe5cc9bbdbd00881556c33d.tar.gz llvm-0082830cb26248178fe5cc9bbdbd00881556c33d.tar.bz2 llvm-0082830cb26248178fe5cc9bbdbd00881556c33d.tar.xz | |
Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127917 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/arm_instructions.s | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s index fbec7891c8..a494081ac6 100644 --- a/test/MC/ARM/arm_instructions.s +++ b/test/MC/ARM/arm_instructions.s @@ -282,3 +282,5 @@ @ CHECK: msr cpsr_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1] msr cpsr_fsxc, r0 +@ CHECK: add r1, r2, r3, lsl r4 @ encoding: [0x13,0x14,0x82,0xe0] + add r1, r2, r3, lsl r4 |