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authorMatt Arsenault <Matthew.Arsenault@amd.com>2014-03-25 16:50:55 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2014-03-25 16:50:55 +0000
commit022746175891fa9d865614f0c435d3d68b3da2cc (patch)
tree6662612348854d25560652f0322916a82bbe66da /test
parentc1c74fb2b4ae2bce68ff1587e3022a158297d936 (diff)
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R600: Add failing testcase for <3 x i32> stores.
This is supposed to have the same store size and alignment as <4 x i32>, but currently is split into a 64-bit and 32-bit store. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204729 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/R600/store-v3i32.ll12
-rw-r--r--test/CodeGen/R600/store-v3i64.ll (renamed from test/CodeGen/R600/store-v3.ll)0
2 files changed, 12 insertions, 0 deletions
diff --git a/test/CodeGen/R600/store-v3i32.ll b/test/CodeGen/R600/store-v3i32.ll
new file mode 100644
index 0000000000..33578035da
--- /dev/null
+++ b/test/CodeGen/R600/store-v3i32.ll
@@ -0,0 +1,12 @@
+; XFAIL: *
+; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+
+; 3 vectors have the same size and alignment as 4 vectors, so this
+; should be done in a single store.
+
+; SI-LABEL: @store_v3i32:
+; SI: BUFFER_STORE_DWORDX4
+define void @store_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a) nounwind {
+ store <3 x i32> %a, <3 x i32> addrspace(1)* %out, align 16
+ ret void
+}
diff --git a/test/CodeGen/R600/store-v3.ll b/test/CodeGen/R600/store-v3i64.ll
index 58229f6048..58229f6048 100644
--- a/test/CodeGen/R600/store-v3.ll
+++ b/test/CodeGen/R600/store-v3i64.ll