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author | Chandler Carruth <chandlerc@gmail.com> | 2014-06-27 11:23:44 +0000 |
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committer | Chandler Carruth <chandlerc@gmail.com> | 2014-06-27 11:23:44 +0000 |
commit | 050d187bc8405bcbb6367a1b22fe253254aff11b (patch) | |
tree | 82f2b84da42b5a897b736d67421331c18f1449b3 /test | |
parent | 3e19a9ee9fbeceabd9be6e72426e7f1e3cfa321f (diff) | |
download | llvm-050d187bc8405bcbb6367a1b22fe253254aff11b.tar.gz llvm-050d187bc8405bcbb6367a1b22fe253254aff11b.tar.bz2 llvm-050d187bc8405bcbb6367a1b22fe253254aff11b.tar.xz |
[x86] Begin a significant overhaul of how vector lowering is done in the
x86 backend.
This sketches out a new code path for vector lowering, hidden behind an
off-by-default flag while it is under development. The fundamental idea
behind the new code path is to aggressively break down the problem space
in ways that ease selecting the odd set of instructions available on
x86, and carefully avoid scalarizing code even when forced to use older
ISAs. Notably, this starts off restricting itself to SSE2 and implements
the complete vector shuffle and blend space for 128-bit vectors in SSE2
without scalarizing. The plan is to layer on top of this ISA extensions
where we can bail out of the complex SSE2 lowering and opt for
a cheaper, specialized instruction (or set of instructions). It also
needs to be generalized to AVX and AVX512 vector widths.
Currently, this does a decent but not perfect job for SSE2. There are
some specific shortcomings that I plan to address:
- We need a peephole combine to fold together shuffles where possible.
There are cases where a previous shuffle could be modified slightly to
arrange for elements to be in the correct position and a later shuffle
eliminated. Doing this eagerly added quite a bit of complexity, and
so my plan is to combine away these redundancies afterward.
- There are a lot more clever ways to use unpck and pack that need to be
added. This is essential for real world shuffles as it turns out...
Once SSE2 is polished a bit I should be able to get interesting numbers
on performance improvements on benchmarks conducive to vectorization.
All of this will be off by default until it is functionally equivalent
of course.
Differential Revision: http://reviews.llvm.org/D4225
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211888 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/X86/vector-shuffle-128-v16.ll | 85 | ||||
-rw-r--r-- | test/CodeGen/X86/vector-shuffle-128-v2.ll | 219 | ||||
-rw-r--r-- | test/CodeGen/X86/vector-shuffle-128-v4.ll | 174 | ||||
-rw-r--r-- | test/CodeGen/X86/vector-shuffle-128-v8.ll | 499 |
4 files changed, 977 insertions, 0 deletions
diff --git a/test/CodeGen/X86/vector-shuffle-128-v16.ll b/test/CodeGen/X86/vector-shuffle-128-v16.ll new file mode 100644 index 0000000000..6203aedcc1 --- /dev/null +++ b/test/CodeGen/X86/vector-shuffle-128-v16.ll @@ -0,0 +1,85 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=CHECK-SSE2 + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-unknown" + +define <16 x i8> @shuffle_v16i8_0101010101010101(<16 x i8> %a, <16 x i8> %b) { +; CHECK-SSE2-LABEL: @shuffle_v16i8_0101010101010101 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm0[0,1,0,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,0,0,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,4,4,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1> + ret <16 x i8> %shuffle +} + +define <16 x i8> @shuffle_v16i8_00_16_01_17_02_18_03_19_04_20_05_21_06_22_07_23(<16 x i8> %a, <16 x i8> %b) { +; CHECK-SSE2-LABEL: @shuffle_v16i8_00_16_01_17_02_18_03_19_04_20_05_21_06_22_07_23 +; CHECK-SSE2: punpcklbw %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> + ret <16 x i8> %shuffle +} + +define <16 x i8> @shuffle_v16i8_16_00_16_01_16_02_16_03_16_04_16_05_16_06_16_07(<16 x i8> %a, <16 x i8> %b) { +; CHECK-SSE2-LABEL: @shuffle_v16i8_16_00_16_01_16_02_16_03_16_04_16_05_16_06_16_07 +; CHECK-SSE2: punpcklbw %xmm0, %xmm1 +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm1 = xmm1[0,1,0,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm1 = xmm1[0,0,0,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm1 = xmm1[0,1,2,3,4,4,4,4] +; CHECK-SSE2-NEXT: packuswb %xmm0, %xmm1 +; CHECK-SSE2-NEXT: punpcklbw %xmm0, %xmm1 +; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 0, i32 16, i32 1, i32 16, i32 2, i32 16, i32 3, i32 16, i32 4, i32 16, i32 5, i32 16, i32 6, i32 16, i32 7> + ret <16 x i8> %shuffle +} + +define <16 x i8> @shuffle_v16i8_03_02_01_00_07_06_05_04_11_10_09_08_15_14_13_12(<16 x i8> %a, <16 x i8> %b) { +; CHECK-SSE2-LABEL: @shuffle_v16i8_03_02_01_00_07_06_05_04_11_10_09_08_15_14_13_12 +; CHECK-SSE2: movdqa %xmm0, %xmm1 +; CHECK-SSE2-NEXT: punpckhbw %xmm0, %xmm1 +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm1 = xmm1[3,2,1,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm1 = xmm1[0,1,2,3,7,6,5,4] +; CHECK-SSE2-NEXT: punpcklbw %xmm0, %xmm0 +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[3,2,1,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,7,6,5,4] +; CHECK-SSE2-NEXT: packuswb %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> + ret <16 x i8> %shuffle +} + +define <16 x i8> @shuffle_v16i8_03_02_01_00_07_06_05_04_19_18_17_16_23_22_21_20(<16 x i8> %a, <16 x i8> %b) { +; CHECK-SSE2-LABEL: @shuffle_v16i8_03_02_01_00_07_06_05_04_19_18_17_16_23_22_21_20 +; CHECK-SSE2: punpcklbw %xmm0, %xmm1 +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm1 = xmm1[3,2,1,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm1 = xmm1[0,1,2,3,7,6,5,4] +; CHECK-SSE2-NEXT: punpcklbw %xmm0, %xmm0 +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[3,2,1,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,7,6,5,4] +; CHECK-SSE2-NEXT: packuswb %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 19, i32 18, i32 17, i32 16, i32 23, i32 22, i32 21, i32 20> + ret <16 x i8> %shuffle +} + +define <16 x i8> @shuffle_v16i8_03_02_01_00_31_30_29_28_11_10_09_08_23_22_21_20(<16 x i8> %a, <16 x i8> %b) { +; CHECK-SSE2-LABEL: @shuffle_v16i8_03_02_01_00_31_30_29_28_11_10_09_08_23_22_21_20 +; CHECK-SSE2: movdqa %xmm1, %xmm2 +; CHECK-SSE2-NEXT: punpcklbw %xmm0, %xmm2 +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm2 = xmm2[0,1,2,3,7,6,5,4] +; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm3 +; CHECK-SSE2-NEXT: punpckhbw %xmm0, %xmm3 +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm3 = xmm3[3,2,1,0,4,5,6,7] +; CHECK-SSE2-NEXT: shufpd {{.*}} # xmm3 = xmm3[0],xmm2[1] +; CHECK-SSE2-NEXT: punpckhbw %xmm0, %xmm1 +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm1 = xmm1[0,1,2,3,7,6,5,4] +; CHECK-SSE2-NEXT: punpcklbw %xmm0, %xmm0 +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[3,2,1,0,4,5,6,7] +; CHECK-SSE2-NEXT: shufpd {{.*}} # xmm0 = xmm0[0],xmm1[1] +; CHECK-SSE2-NEXT: packuswb %xmm3, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 31, i32 30, i32 29, i32 28, i32 11, i32 10, i32 9, i32 8, i32 23, i32 22, i32 21, i32 20> + ret <16 x i8> %shuffle +} diff --git a/test/CodeGen/X86/vector-shuffle-128-v2.ll b/test/CodeGen/X86/vector-shuffle-128-v2.ll new file mode 100644 index 0000000000..78b4ee7e5d --- /dev/null +++ b/test/CodeGen/X86/vector-shuffle-128-v2.ll @@ -0,0 +1,219 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=CHECK-SSE2 + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-unknown" + +define <2 x i64> @shuffle_v2i64_00(<2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_00 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm0[0,1,0,1] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 0> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_10(<2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_10 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm0[2,3,0,1] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 0> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_11(<2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_11 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm0[2,3,2,3] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 1> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_22(<2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_22 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm1[0,1,0,1] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 2, i32 2> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_32(<2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_32 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm1[2,3,0,1] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 2> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_33(<2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_33 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm1[2,3,2,3] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 3> + ret <2 x i64> %shuffle +} + +define <2 x double> @shuffle_v2f64_00(<2 x double> %a, <2 x double> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2f64_00 +; CHECK-SSE2: shufpd {{.*}} # xmm0 = xmm0[0,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0> + ret <2 x double> %shuffle +} +define <2 x double> @shuffle_v2f64_10(<2 x double> %a, <2 x double> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2f64_10 +; CHECK-SSE2: shufpd {{.*}} # xmm0 = xmm0[1,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 0> + ret <2 x double> %shuffle +} +define <2 x double> @shuffle_v2f64_11(<2 x double> %a, <2 x double> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2f64_11 +; CHECK-SSE2: shufpd {{.*}} # xmm0 = xmm0[1,1] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 1> + ret <2 x double> %shuffle +} +define <2 x double> @shuffle_v2f64_22(<2 x double> %a, <2 x double> %b) { +; FIXME: Should these use movapd + shufpd to remove a domain change at the cost +; of a mov? +; +; CHECK-SSE2-LABEL: @shuffle_v2f64_22 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm1[0,1,0,1] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 2> + ret <2 x double> %shuffle +} +define <2 x double> @shuffle_v2f64_32(<2 x double> %a, <2 x double> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2f64_32 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm1[2,3,0,1] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 3, i32 2> + ret <2 x double> %shuffle +} +define <2 x double> @shuffle_v2f64_33(<2 x double> %a, <2 x double> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2f64_33 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm1[2,3,2,3] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 3, i32 3> + ret <2 x double> %shuffle +} + + +define <2 x i64> @shuffle_v2i64_02(<2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_02 +; CHECK-SSE2: shufpd {{.*}} # xmm0 = xmm0[0],xmm1[0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_02_copy(<2 x i64> %nonce, <2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_02_copy +; CHECK-SSE2: shufpd {{.*}} # xmm1 = xmm1[0],xmm2[0] +; CHECK-SSE2-NEXT: movapd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_03(<2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_03 +; CHECK-SSE2: shufpd {{.*}} # xmm0 = xmm0[0],xmm1[1] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 3> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_03_copy(<2 x i64> %nonce, <2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_03_copy +; CHECK-SSE2: shufpd {{.*}} # xmm1 = xmm1[0],xmm2[1] +; CHECK-SSE2-NEXT: movapd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 3> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_12(<2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_12 +; CHECK-SSE2: shufpd {{.*}} # xmm0 = xmm0[1],xmm1[0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_12_copy(<2 x i64> %nonce, <2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_12_copy +; CHECK-SSE2: shufpd {{.*}} # xmm1 = xmm1[1],xmm2[0] +; CHECK-SSE2-NEXT: movapd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_13(<2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_13 +; CHECK-SSE2: shufpd {{.*}} # xmm0 = xmm0[1],xmm1[1] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_13_copy(<2 x i64> %nonce, <2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_13_copy +; CHECK-SSE2: shufpd {{.*}} # xmm1 = xmm1[1],xmm2[1] +; CHECK-SSE2-NEXT: movapd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_20(<2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_20 +; CHECK-SSE2: shufpd {{.*}} # xmm1 = xmm1[0],xmm0[0] +; CHECK-SSE2-NEXT: movapd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 2, i32 0> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_20_copy(<2 x i64> %nonce, <2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_20_copy +; CHECK-SSE2: shufpd {{.*}} # xmm2 = xmm2[0],xmm1[0] +; CHECK-SSE2-NEXT: movapd %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 2, i32 0> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_21(<2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_21 +; CHECK-SSE2: shufpd {{.*}} # xmm1 = xmm1[0],xmm0[1] +; CHECK-SSE2-NEXT: movapd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 2, i32 1> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_21_copy(<2 x i64> %nonce, <2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_21_copy +; CHECK-SSE2: shufpd {{.*}} # xmm2 = xmm2[0],xmm1[1] +; CHECK-SSE2-NEXT: movapd %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 2, i32 1> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_30(<2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_30 +; CHECK-SSE2: shufpd {{.*}} # xmm1 = xmm1[1],xmm0[0] +; CHECK-SSE2-NEXT: movapd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 0> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_30_copy(<2 x i64> %nonce, <2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_30_copy +; CHECK-SSE2: shufpd {{.*}} # xmm2 = xmm2[1],xmm1[0] +; CHECK-SSE2-NEXT: movapd %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 0> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_31(<2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_31 +; CHECK-SSE2: shufpd {{.*}} # xmm1 = xmm1[1],xmm0[1] +; CHECK-SSE2-NEXT: movapd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 1> + ret <2 x i64> %shuffle +} +define <2 x i64> @shuffle_v2i64_31_copy(<2 x i64> %nonce, <2 x i64> %a, <2 x i64> %b) { +; CHECK-SSE2-LABEL: @shuffle_v2i64_31_copy +; CHECK-SSE2: shufpd {{.*}} # xmm2 = xmm2[1],xmm1[1] +; CHECK-SSE2-NEXT: movapd %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 1> + ret <2 x i64> %shuffle +} diff --git a/test/CodeGen/X86/vector-shuffle-128-v4.ll b/test/CodeGen/X86/vector-shuffle-128-v4.ll new file mode 100644 index 0000000000..d7899f0db4 --- /dev/null +++ b/test/CodeGen/X86/vector-shuffle-128-v4.ll @@ -0,0 +1,174 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=CHECK-SSE2 + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-unknown" + +define <4 x i32> @shuffle_v4i32_0001(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_0001 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm0[0,0,0,1] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1> + ret <4 x i32> %shuffle +} +define <4 x i32> @shuffle_v4i32_0020(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_0020 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm0[0,0,2,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0> + ret <4 x i32> %shuffle +} +define <4 x i32> @shuffle_v4i32_0300(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_0300 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm0[0,3,0,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0> + ret <4 x i32> %shuffle +} +define <4 x i32> @shuffle_v4i32_1000(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_1000 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm0[1,0,0,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0> + ret <4 x i32> %shuffle +} +define <4 x i32> @shuffle_v4i32_2200(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_2200 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm0[2,2,0,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0> + ret <4 x i32> %shuffle +} +define <4 x i32> @shuffle_v4i32_3330(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_3330 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm0[3,3,3,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0> + ret <4 x i32> %shuffle +} +define <4 x i32> @shuffle_v4i32_3210(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_3210 +; CHECK-SSE2: pshufd {{.*}} # xmm0 = xmm0[3,2,1,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0> + ret <4 x i32> %shuffle +} + +define <4 x float> @shuffle_v4f32_0001(<4 x float> %a, <4 x float> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4f32_0001 +; CHECK-SSE2: shufps {{.*}} # xmm0 = xmm0[0,0,0,1] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_0020(<4 x float> %a, <4 x float> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4f32_0020 +; CHECK-SSE2: shufps {{.*}} # xmm0 = xmm0[0,0,2,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_0300(<4 x float> %a, <4 x float> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4f32_0300 +; CHECK-SSE2: shufps {{.*}} # xmm0 = xmm0[0,3,0,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_1000(<4 x float> %a, <4 x float> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4f32_1000 +; CHECK-SSE2: shufps {{.*}} # xmm0 = xmm0[1,0,0,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_2200(<4 x float> %a, <4 x float> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4f32_2200 +; CHECK-SSE2: shufps {{.*}} # xmm0 = xmm0[2,2,0,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_3330(<4 x float> %a, <4 x float> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4f32_3330 +; CHECK-SSE2: shufps {{.*}} # xmm0 = xmm0[3,3,3,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0> + ret <4 x float> %shuffle +} +define <4 x float> @shuffle_v4f32_3210(<4 x float> %a, <4 x float> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4f32_3210 +; CHECK-SSE2: shufps {{.*}} # xmm0 = xmm0[3,2,1,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0> + ret <4 x float> %shuffle +} + +define <4 x i32> @shuffle_v4i32_0124(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_0124 +; CHECK-SSE2: shufps {{.*}} # xmm1 = xmm1[0,0],xmm0[2,0] +; CHECK-SSE2-NEXT: shufps {{.*}} # xmm0 = xmm0[0,1],xmm1[2,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4> + ret <4 x i32> %shuffle +} +define <4 x i32> @shuffle_v4i32_0142(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_0142 +; CHECK-SSE2: shufps {{.*}} # xmm1 = xmm1[0,0],xmm0[2,0] +; CHECK-SSE2-NEXT: shufps {{.*}} # xmm0 = xmm0[0,1],xmm1[0,2] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 2> + ret <4 x i32> %shuffle +} +define <4 x i32> @shuffle_v4i32_0412(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_0412 +; CHECK-SSE2: shufps {{.*}} # xmm1 = xmm1[0,0],xmm0[0,0] +; CHECK-SSE2-NEXT: shufps {{.*}} # xmm1 = xmm1[2,0],xmm0[1,2] +; CHECK-SSE2-NEXT: movaps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 2> + ret <4 x i32> %shuffle +} +define <4 x i32> @shuffle_v4i32_4012(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_4012 +; CHECK-SSE2: shufps {{.*}} # xmm1 = xmm1[0,0],xmm0[0,0] +; CHECK-SSE2-NEXT: shufps {{.*}} # xmm1 = xmm1[0,2],xmm0[1,2] +; CHECK-SSE2-NEXT: movaps %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 0, i32 1, i32 2> + ret <4 x i32> %shuffle +} +define <4 x i32> @shuffle_v4i32_0145(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_0145 +; CHECK-SSE2: shufpd {{.*}} # xmm0 = xmm0[0],xmm1[0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5> + ret <4 x i32> %shuffle +} +define <4 x i32> @shuffle_v4i32_0451(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_0451 +; CHECK-SSE2: movaps %xmm0, %xmm2 +; CHECK-SSE2-NEXT: shufps {{.*}} # xmm2 = xmm2[0,1],xmm1[0,1] +; FIXME: This is wrong!!! xmm0 = xmm2[0,2],xmm2[3,1] would be correct.... +; CHECK-SSE2-NEXT: shufps {{.*}} # xmm0 = xmm0[0,2],xmm2[3,1] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 1> + ret <4 x i32> %shuffle +} +define <4 x i32> @shuffle_v4i32_4501(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_4501 +; CHECK-SSE2: shufpd {{.*}} # xmm1 = xmm1[0],xmm0[0] +; CHECK-SSE2-NEXT: movapd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1> + ret <4 x i32> %shuffle +} +define <4 x i32> @shuffle_v4i32_4015(<4 x i32> %a, <4 x i32> %b) { +; CHECK-SSE2-LABEL: @shuffle_v4i32_4015 +; CHECK-SSE2: movaps %xmm0, %xmm2 +; CHECK-SSE2-NEXT: shufps {{.*}} # xmm2 = xmm2[0,1],xmm1[0,1] +; FIXME: This is wrong!!! xmm0 = xmm2[0,2],xmm2[3,1] would be correct.... +; CHECK-SSE2-NEXT: shufps {{.*}} # xmm0 = xmm0[2,0],xmm2[1,3] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 0, i32 1, i32 5> + ret <4 x i32> %shuffle +} diff --git a/test/CodeGen/X86/vector-shuffle-128-v8.ll b/test/CodeGen/X86/vector-shuffle-128-v8.ll new file mode 100644 index 0000000000..7447fdc874 --- /dev/null +++ b/test/CodeGen/X86/vector-shuffle-128-v8.ll @@ -0,0 +1,499 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=CHECK-SSE2 + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-unknown" + +define <8 x i16> @shuffle_v8i16_01012323(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_01012323 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,0,1,1] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_67452301(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_67452301 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[3,2,1,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 2, i32 3, i32 0, i32 1> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_456789AB(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_456789AB +; CHECK-SSE2: # BB#0: +; CHECK-SSE2: shufpd {{.*}} # xmm0 = xmm0[1],xmm1[0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_00000000(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_00000000 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,1,0,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,0,0,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,4,4,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_00004444(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_00004444 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,0,0,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,4,4,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_31206745(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_31206745 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[3,1,2,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,6,7,4,5] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 1, i32 2, i32 0, i32 6, i32 7, i32 4, i32 5> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_44440000(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_44440000 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[2,1,0,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,0,0,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,4,4,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 4, i32 4, i32 4, i32 0, i32 0, i32 0, i32 0> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_75643120(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_75643120 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[2,3,0,1] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[3,1,2,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,7,5,6,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 7, i32 5, i32 6, i32 4, i32 3, i32 1, i32 2, i32 0> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_10545410(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_10545410 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,0] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[1,0,3,2,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,5,4,7,6] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 0, i32 5, i32 4, i32 5, i32 4, i32 1, i32 0> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_54105410(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_54105410 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,0] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[3,2,1,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,5,4,7,6] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 5, i32 4, i32 1, i32 0, i32 5, i32 4, i32 1, i32 0> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_54101054(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_54101054 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,0] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[3,2,1,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,7,6,5,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 5, i32 4, i32 1, i32 0, i32 1, i32 0, i32 5, i32 4> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_04400440(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_04400440 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,0] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,2,2,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,6,4,4,6] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 4, i32 4, i32 0, i32 0, i32 4, i32 4, i32 0> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_40044004(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_40044004 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,0] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[2,0,0,2,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,6,6,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 0, i32 0, i32 4, i32 4, i32 0, i32 0, i32 4> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_26405173(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_26405173 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,2,1,3,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,7,5,4,6] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,3,2,1] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[1,3,2,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,5,6,4,7] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 2, i32 6, i32 4, i32 0, i32 5, i32 1, i32 7, i32 3> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_20645173(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_20645173 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,2,1,3,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,7,5,4,6] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,3,2,1] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[1,0,3,2,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,5,6,4,7] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 2, i32 0, i32 6, i32 4, i32 5, i32 1, i32 7, i32 3> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_26401375(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_26401375 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,2,1,3,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,7,5,4,6] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,3,2,1] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[1,3,2,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,6,7,4,5] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 2, i32 6, i32 4, i32 0, i32 1, i32 3, i32 7, i32 5> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_00444444(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_00444444 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,0,2,2,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,4,4,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 0, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_44004444(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_44004444 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[2,2,0,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,4,4,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 4, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_04404444(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_04404444 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,2,2,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,4,4,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 4, i32 4, i32 0, i32 4, i32 4, i32 4, i32 4> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_04400000(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_04400000 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,0,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,2,2,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,4,4,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 4, i32 4, i32 0, i32 0, i32 0, i32 0, i32 0> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_04404567(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_04404567 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,2,2,0,4,5,6,7] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 4, i32 4, i32 0, i32 4, i32 5, i32 6, i32 7> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_0X444444(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_0X444444 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,1,2,2,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,4,4,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 undef, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_44X04444(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_44X04444 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[2,2,2,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,4,4,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 4, i32 undef, i32 0, i32 4, i32 4, i32 4, i32 4> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_X4404444(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_X4404444 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,2,2,0,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,4,4,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 undef, i32 4, i32 4, i32 0, i32 4, i32 4, i32 4, i32 4> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_0127XXXX(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_0127XXXX +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,1,3] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,7,6,7] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,3] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 7, i32 undef, i32 undef, i32 undef, i32 undef> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_XXXX4563(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_XXXX4563 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[3,1,2,0] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,3,2,3,4,5,6,7] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,1,2,0] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 4, i32 5, i32 6, i32 3> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_4563XXXX(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_4563XXXX +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[3,1,2,0] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,3,2,3,4,5,6,7] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[2,3,0,1,4,5,6,7] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_01274563(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_01274563 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,1,3] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,6,5,4,7] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,3,2,1] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,6,7,4,5] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 3> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_45630127(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_45630127 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[3,1,2,0] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,3,1,2,4,5,6,7] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,1,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[2,3,0,1,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,6,7,5,4] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 3, i32 0, i32 1, i32 2, i32 7> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_08192a3b(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_08192a3b +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: punpcklwd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_0c1d2e3f(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_0c1d2e3f +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm1 = xmm1[2,3,2,3] +; CHECK-SSE2-NEXT: punpcklwd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 12, i32 1, i32 13, i32 2, i32 14, i32 3, i32 15> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_4c5d6e7f(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_4c5d6e7f +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm1 = xmm1[2,3,2,3] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[2,3,2,3] +; CHECK-SSE2-NEXT: punpcklwd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_48596a7b(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_48596a7b +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[2,3,2,3] +; CHECK-SSE2-NEXT: punpcklwd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 8, i32 5, i32 9, i32 6, i32 10, i32 7, i32 11> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_08196e7f(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_08196e7f +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm1 = xmm1[0,3,2,3] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,3,2,3] +; CHECK-SSE2-NEXT: punpcklwd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 6, i32 14, i32 7, i32 15> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_0c1d6879(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_0c1d6879 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,3,2,3] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm1 = xmm1[0,2,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm1 = xmm1[2,3,0,1,4,5,6,7] +; CHECK-SSE2-NEXT: punpcklwd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 12, i32 1, i32 13, i32 6, i32 8, i32 7, i32 9> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_109832ba(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_109832ba +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: punpcklwd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm1 = xmm0[2,0,3,1,4,5,6,7] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[2,3,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[2,0,3,1,4,5,6,7] +; CHECK-SSE2-NEXT: punpcklqdq %xmm0, %xmm1 +; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 0, i32 9, i32 8, i32 3, i32 2, i32 11, i32 10> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_8091a2b3(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_8091a2b3 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: punpcklwd %xmm0, %xmm1 +; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_c4d5e6f7(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_c4d5e6f7 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm2 = xmm0[2,3,2,3] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm1[2,3,2,3] +; CHECK-SSE2-NEXT: punpcklwd %xmm2, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 12, i32 4, i32 13, i32 5, i32 14, i32 6, i32 15, i32 7> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_0213cedf(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_0213cedf +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,2,1,3,4,5,6,7] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm1 = xmm1[2,3,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm1 = xmm1[0,2,1,3,4,5,6,7] +; CHECK-SSE2-NEXT: punpcklqdq %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 2, i32 1, i32 3, i32 12, i32 14, i32 13, i32 15> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_032dXXXX(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_032dXXXX +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm1 = xmm1[2,1,2,3] +; CHECK-SSE2-NEXT: punpcklwd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,3,2,3,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,6,6,7] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,3,2,1,4,5,6,7] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 3, i32 2, i32 13, i32 undef, i32 undef, i32 undef, i32 undef> + ret <8 x i16> %shuffle +} +define <8 x i16> @shuffle_v8i16_XXXcXXXX(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_XXXcXXXX +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm1[2,1,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[0,1,2,1,4,5,6,7] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 13, i32 undef, i32 undef, i32 undef, i32 undef> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_012dXXXX(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_012dXXXX +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm1 = xmm1[2,1,2,3] +; CHECK-SSE2-NEXT: punpcklwd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[3,1,2,0] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,6,6,7] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[2,1,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[1,2,0,3,4,5,6,7] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 undef, i32 undef, i32 undef, i32 undef> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_XXXXcde3(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_XXXXcde3 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,1,2,1] +; CHECK-SSE2-NEXT: punpckhwd %xmm0, %xmm1 +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm1[0,2,2,3,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,7,6,7] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,1,2,0] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,6,7,4,5] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 3> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_cde3XXXX(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_cde3XXXX +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,1,2,1] +; CHECK-SSE2-NEXT: punpckhwd %xmm0, %xmm1 +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm1[0,2,2,3,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,7,6,7] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[0,2,2,3] +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 12, i32 13, i32 14, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> + ret <8 x i16> %shuffle +} + +define <8 x i16> @shuffle_v8i16_012dcde3(<8 x i16> %a, <8 x i16> %b) { +; CHECK-SSE2-LABEL: @shuffle_v8i16_012dcde3 +; CHECK-SSE2: # BB#0: +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm2 = xmm0[0,1,2,1] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm3 = xmm1[2,1,2,3] +; CHECK-SSE2-NEXT: punpckhwd %xmm2, %xmm1 +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm1 = xmm1[0,2,2,3,4,5,6,7] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm1 = xmm1[0,1,2,3,4,7,6,7] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm1 = xmm1[0,2,2,3] +; CHECK-SSE2-NEXT: punpcklwd %xmm3, %xmm0 +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[3,1,2,0] +; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,4,6,6,7] +; CHECK-SSE2-NEXT: pshufd {{.*}} # xmm0 = xmm0[2,1,2,3] +; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[1,2,0,3,4,5,6,7] +; CHECK-SSE2-NEXT: punpcklqdq %xmm1, %xmm0 +; CHECK-SSE2-NEXT: retq + %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 12, i32 13, i32 14, i32 3> + ret <8 x i16> %shuffle +} |