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authorOwen Anderson <resistor@mac.com>2012-04-10 22:46:53 +0000
committerOwen Anderson <resistor@mac.com>2012-04-10 22:46:53 +0000
commit06886aaaebe38b7e4b253b336624c9a7ab6dbc44 (patch)
tree98d78fee2125b594e2037ae3a9659d771ed75caa /test
parent83f17f25fc560db4f756010a1bbe1f8eb1d74b12 (diff)
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Move the constant-folding support for FP_ROUND in SelectionDAG from the one-operand version of getNode() to the two-operand version, since it became a two-operand node at sound point.
Zap a testcase that this allows us to completely fold away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154447 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/ARM/fcopysign.ll20
1 files changed, 2 insertions, 18 deletions
diff --git a/test/CodeGen/ARM/fcopysign.ll b/test/CodeGen/ARM/fcopysign.ll
index 87115ccbc8..27fa2b093d 100644
--- a/test/CodeGen/ARM/fcopysign.ll
+++ b/test/CodeGen/ARM/fcopysign.ll
@@ -40,26 +40,10 @@ entry:
ret double %1
}
-; rdar://9059537
-define i32 @test4() ssp {
-entry:
-; SOFT: test4:
-; SOFT: vmov.f64 [[REG4:(d[0-9]+)]], #1.000000e+00
-; This S-reg must be the first sub-reg of the last D-reg on vbsl.
-; SOFT: vcvt.f32.f64 {{s1?[02468]}}, [[REG4]]
-; SOFT: vshr.u64 [[REG4]], [[REG4]], #32
-; SOFT: vmov.i32 [[REG5:(d[0-9]+)]], #0x80000000
-; SOFT: vbsl [[REG5]], [[REG4]], {{d[0-9]+}}
- %call80 = tail call double @copysign(double 1.000000e+00, double undef)
- %conv81 = fptrunc double %call80 to float
- %tmp88 = bitcast float %conv81 to i32
- ret i32 %tmp88
-}
-
; rdar://9287902
-define float @test5() nounwind {
+define float @test4() nounwind {
entry:
-; SOFT: test5:
+; SOFT: test4:
; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1
; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
; SOFT: vshr.u64 [[REG7]], [[REG7]], #32