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authorNadav Rotem <nadav.rotem@intel.com>2011-06-04 20:58:08 +0000
committerNadav Rotem <nadav.rotem@intel.com>2011-06-04 20:58:08 +0000
commit0b66636879bc478781ea6ed7541cdc1d13ee714d (patch)
tree0b8ee6705eff56dbe8d1b6967b4de4e64b8e6c18 /test
parentf1c025d1d106905df3d38d2482fde68c8f81b107 (diff)
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TypeLegalizer: Add support for passing of vector-promoted types in registers (copyFromParts/copyToParts).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132649 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/Generic/basic-promote-integers.ll20
1 files changed, 20 insertions, 0 deletions
diff --git a/test/CodeGen/Generic/basic-promote-integers.ll b/test/CodeGen/Generic/basic-promote-integers.ll
new file mode 100644
index 0000000000..13402bfd58
--- /dev/null
+++ b/test/CodeGen/Generic/basic-promote-integers.ll
@@ -0,0 +1,20 @@
+; Test that vectors are scalarized/lowered correctly
+; (with both legalization methods).
+; RUN: llc -march=x86 -promote-elements < %s
+; RUN: llc -march=x86 < %s
+
+; A simple test to check copyToParts and copyFromParts
+
+define <4 x i64> @test_param_0(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) {
+ ret <4 x i64> %A
+}
+
+define <2 x i32> @test_param_1(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) {
+ ret <2 x i32> %B
+}
+
+define <4 x i8> @test_param_2(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) {
+ ret <4 x i8> %C
+}
+
+