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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-06-18 16:49:33 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-06-18 16:49:33 +0000 |
| commit | 0d8ba3303b40a150f70ff63f04f57160984492c1 (patch) | |
| tree | 2952503264472bde1a949b267a3d0ae8785026ab /test | |
| parent | 45934330150aecbc98c2d60fe7f17fa69e62ba71 (diff) | |
| download | llvm-0d8ba3303b40a150f70ff63f04f57160984492c1.tar.gz llvm-0d8ba3303b40a150f70ff63f04f57160984492c1.tar.bz2 llvm-0d8ba3303b40a150f70ff63f04f57160984492c1.tar.xz | |
Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/crash-O0.ll | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/crash-O0.ll b/test/CodeGen/ARM/crash-O0.ll new file mode 100644 index 0000000000..4f0f39fe38 --- /dev/null +++ b/test/CodeGen/ARM/crash-O0.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "armv6-apple-darwin10" + +%struct0 = type { i32, i32 } + +; This function would crash RegAllocFast because it tried to spill %CPSR. +define arm_apcscc void @clobber_cc() nounwind noinline ssp { +entry: + %asmtmp = call %struct0 asm sideeffect "...", "=&r,=&r,r,Ir,r,~{cc},~{memory}"(i32* undef, i32 undef, i32 1) nounwind ; <%0> [#uses=0] + unreachable +} |