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| author | Justin Holewinski <jholewinski@nvidia.com> | 2013-06-21 18:51:49 +0000 |
|---|---|---|
| committer | Justin Holewinski <jholewinski@nvidia.com> | 2013-06-21 18:51:49 +0000 |
| commit | 0ff4287fe2245f417ed78fa535fce360b8b8df23 (patch) | |
| tree | e70770e354d723b8320b18a505138396f514a9ee /test | |
| parent | c22e02b1f41387e791a08f1715e877e4fd86ca87 (diff) | |
| download | llvm-0ff4287fe2245f417ed78fa535fce360b8b8df23.tar.gz llvm-0ff4287fe2245f417ed78fa535fce360b8b8df23.tar.bz2 llvm-0ff4287fe2245f417ed78fa535fce360b8b8df23.tar.xz | |
[NVPTX] Add support for selecting CUDA vs OCL mode based on triple
IR for CUDA should use "nvptx[64]-nvidia-cuda", and IR for NV OpenCL should use "nvptx[64]-nvidia-nvcl"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184579 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/NVPTX/generic-to-nvvm.ll | 3 | ||||
| -rw-r--r-- | test/CodeGen/NVPTX/i1-global.ll | 4 | ||||
| -rw-r--r-- | test/CodeGen/NVPTX/i1-param.ll | 3 | ||||
| -rw-r--r-- | test/CodeGen/NVPTX/load-sext-i1.ll | 4 | ||||
| -rw-r--r-- | test/CodeGen/NVPTX/refl1.ll | 4 |
5 files changed, 11 insertions, 7 deletions
diff --git a/test/CodeGen/NVPTX/generic-to-nvvm.ll b/test/CodeGen/NVPTX/generic-to-nvvm.ll index c9cb2f71f4..2a527989e4 100644 --- a/test/CodeGen/NVPTX/generic-to-nvvm.ll +++ b/test/CodeGen/NVPTX/generic-to-nvvm.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" +target triple = "nvptx-nvidia-cuda" ; Ensure global variables in address space 0 are promoted to address space 1 diff --git a/test/CodeGen/NVPTX/i1-global.ll b/test/CodeGen/NVPTX/i1-global.ll index 0595325977..1dd8ae40db 100644 --- a/test/CodeGen/NVPTX/i1-global.ll +++ b/test/CodeGen/NVPTX/i1-global.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" - +target triple = "nvptx-nvidia-cuda" ; CHECK: .visible .global .align 1 .u8 mypred @mypred = addrspace(1) global i1 true, align 1 diff --git a/test/CodeGen/NVPTX/i1-param.ll b/test/CodeGen/NVPTX/i1-param.ll index fabd61a25d..f4df874393 100644 --- a/test/CodeGen/NVPTX/i1-param.ll +++ b/test/CodeGen/NVPTX/i1-param.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" +target triple = "nvptx-nvidia-cuda" ; Make sure predicate (i1) operands to kernels get expanded out to .u8 diff --git a/test/CodeGen/NVPTX/load-sext-i1.ll b/test/CodeGen/NVPTX/load-sext-i1.ll index c9b2e9793b..d836740eed 100644 --- a/test/CodeGen/NVPTX/load-sext-i1.ll +++ b/test/CodeGen/NVPTX/load-sext-i1.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" - +target triple = "nvptx-nvidia-cuda" define void @main(i1* %a1, i32 %a2, i32* %arg3) { ; CHECK: ld.u8 diff --git a/test/CodeGen/NVPTX/refl1.ll b/test/CodeGen/NVPTX/refl1.ll index 5a9dac152e..4aeff09249 100644 --- a/test/CodeGen/NVPTX/refl1.ll +++ b/test/CodeGen/NVPTX/refl1.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s + +target triple = "nvptx-nvidia-cuda" ; Function Attrs: nounwind ; CHECK: .entry foo |