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author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-01-28 18:14:21 +0000 |
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committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-01-28 18:14:21 +0000 |
commit | 106b79744b185969faf8a74c6bd7cad35e6f11bd (patch) | |
tree | 4c15347510f68dd40e18caff39499634243557a1 /test | |
parent | bb6f2367296bf6e78049ff32e7fa4f7c96d80a47 (diff) | |
download | llvm-106b79744b185969faf8a74c6bd7cad35e6f11bd.tar.gz llvm-106b79744b185969faf8a74c6bd7cad35e6f11bd.tar.bz2 llvm-106b79744b185969faf8a74c6bd7cad35e6f11bd.tar.xz |
[X86] Add extra rules for combining vselect dag nodes into movsd.
This improves the fix committed at revision 199683 adding the
following new target specific combine rules:
1) fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
(v4i32 (bitcast (movsd (v2i64 (bitcast A)), (v2i64 (bitcast B))) ))
2) fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
(v4f32 (bitcast (movsd (v2f64 (bitcast A)), (v2f64 (bitcast B))) ))
3) fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
(v4i32 (bitcast (movsd (v2i64 (bitcast B)), (v2i64 (bitcast A))) ))
4) fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
(v4f32 (bitcast (movsd (v2i64 (bitcast B)), (v2i64 (bitcast A))) ))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200324 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/X86/sse41-blend.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/X86/vselect-2.ll | 33 |
2 files changed, 35 insertions, 2 deletions
diff --git a/test/CodeGen/X86/sse41-blend.ll b/test/CodeGen/X86/sse41-blend.ll index 597852c369..4681fde754 100644 --- a/test/CodeGen/X86/sse41-blend.ll +++ b/test/CodeGen/X86/sse41-blend.ll @@ -13,7 +13,7 @@ define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) { ;CHECK: blendvps ;CHECK: ret define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) { - %vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i8> %v1, <4 x i8> %v2 + %vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i8> %v1, <4 x i8> %v2 ret <4 x i8> %vsel } @@ -30,7 +30,7 @@ define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) { ;CHECK: blendvps ;CHECK: ret define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) { - %vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i32> %v1, <4 x i32> %v2 + %vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i32> %v1, <4 x i32> %v2 ret <4 x i32> %vsel } diff --git a/test/CodeGen/X86/vselect-2.ll b/test/CodeGen/X86/vselect-2.ll new file mode 100644 index 0000000000..50da32c67a --- /dev/null +++ b/test/CodeGen/X86/vselect-2.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=sse2 | FileCheck %s + +define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) { + %select = select <4 x i1><i1 true, i1 true, i1 false, i1 false>, <4 x i32> %A, <4 x i32> %B + ret <4 x i32> %select +} +; CHECK-LABEL: test1 +; CHECK: movsd +; CHECK: ret + +define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) { + %select = select <4 x i1><i1 false, i1 false, i1 true, i1 true>, <4 x i32> %A, <4 x i32> %B + ret <4 x i32> %select +} +; CHECK-LABEL: test2 +; CHECK: movsd +; CHECK-NEXT: ret + +define <4 x float> @test3(<4 x float> %A, <4 x float> %B) { + %select = select <4 x i1><i1 true, i1 true, i1 false, i1 false>, <4 x float> %A, <4 x float> %B + ret <4 x float> %select +} +; CHECK-LABEL: test3 +; CHECK: movsd +; CHECK: ret + +define <4 x float> @test4(<4 x float> %A, <4 x float> %B) { + %select = select <4 x i1><i1 false, i1 false, i1 true, i1 true>, <4 x float> %A, <4 x float> %B + ret <4 x float> %select +} +; CHECK-LABEL: test4 +; CHECK: movsd +; CHECK-NEXT: ret |