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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-07-01 21:40:54 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-07-01 21:40:54 +0000 |
| commit | 1307d8300f6fe97059998480c42b44faefbc9b99 (patch) | |
| tree | aa96625b4ffc7739df065a5b144ffc610c1a7d2b /test | |
| parent | bde84a96ea67737e275d2adee2da86a0fa875785 (diff) | |
| download | llvm-1307d8300f6fe97059998480c42b44faefbc9b99.tar.gz llvm-1307d8300f6fe97059998480c42b44faefbc9b99.tar.bz2 llvm-1307d8300f6fe97059998480c42b44faefbc9b99.tar.xz | |
[PowerPC] Support all condition register logical instructions
This adds support for all missing condition register logical
instructions and extended mnemonics to the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185387 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/PowerPC/ppc64-encoding-ext.s | 11 | ||||
| -rw-r--r-- | test/MC/PowerPC/ppc64-encoding.s | 18 |
2 files changed, 22 insertions, 7 deletions
diff --git a/test/MC/PowerPC/ppc64-encoding-ext.s b/test/MC/PowerPC/ppc64-encoding-ext.s index 9f1d1c8aa7..d2288a55cb 100644 --- a/test/MC/PowerPC/ppc64-encoding-ext.s +++ b/test/MC/PowerPC/ppc64-encoding-ext.s @@ -1786,7 +1786,16 @@ # CHECK: bnuctrl- 0 # encoding: [0x4c,0xc3,0x04,0x21] bnuctrl- -# FIXME: Condition register logical mnemonics +# Condition register logical mnemonics + +# CHECK: creqv 2, 2, 2 # encoding: [0x4c,0x42,0x12,0x42] + crset 2 +# CHECK: crxor 2, 2, 2 # encoding: [0x4c,0x42,0x11,0x82] + crclr 2 +# CHECK: cror 2, 3, 3 # encoding: [0x4c,0x43,0x1b,0x82] + crmove 2, 3 +# CHECK: crnor 2, 3, 3 # encoding: [0x4c,0x43,0x18,0x42] + crnot 2, 3 # Subtract mnemonics diff --git a/test/MC/PowerPC/ppc64-encoding.s b/test/MC/PowerPC/ppc64-encoding.s index edf18eb96a..fcf2407abe 100644 --- a/test/MC/PowerPC/ppc64-encoding.s +++ b/test/MC/PowerPC/ppc64-encoding.s @@ -50,16 +50,22 @@ # Condition register instructions -# FIXME: crand 2, 3, 4 -# FIXME: crnand 2, 3, 4 +# CHECK: crand 2, 3, 4 # encoding: [0x4c,0x43,0x22,0x02] + crand 2, 3, 4 +# CHECK: crnand 2, 3, 4 # encoding: [0x4c,0x43,0x21,0xc2] + crnand 2, 3, 4 # CHECK: cror 2, 3, 4 # encoding: [0x4c,0x43,0x23,0x82] cror 2, 3, 4 -# FIXME: crxor 2, 3, 4 -# FIXME: crnor 2, 3, 4 +# CHECK: crxor 2, 3, 4 # encoding: [0x4c,0x43,0x21,0x82] + crxor 2, 3, 4 +# CHECK: crnor 2, 3, 4 # encoding: [0x4c,0x43,0x20,0x42] + crnor 2, 3, 4 # CHECK: creqv 2, 3, 4 # encoding: [0x4c,0x43,0x22,0x42] creqv 2, 3, 4 -# FIXME: crandc 2, 3, 4 -# FIXME: crorc 2, 3, 4 +# CHECK: crandc 2, 3, 4 # encoding: [0x4c,0x43,0x21,0x02] + crandc 2, 3, 4 +# CHECK: crorc 2, 3, 4 # encoding: [0x4c,0x43,0x23,0x42] + crorc 2, 3, 4 # CHECK: mcrf 2, 3 # encoding: [0x4d,0x0c,0x00,0x00] mcrf 2, 3 |