diff options
| author | Eric Christopher <echristo@gmail.com> | 2013-09-04 21:23:23 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@gmail.com> | 2013-09-04 21:23:23 +0000 |
| commit | 1b290a139ad707585ecb3da46d13e294546395a5 (patch) | |
| tree | ed0b49ff1b35ac2982aac58678fa89de40ef2738 /test | |
| parent | 3d6e70c857ded2605699f7de1b18269f4fb390bf (diff) | |
| download | llvm-1b290a139ad707585ecb3da46d13e294546395a5.tar.gz llvm-1b290a139ad707585ecb3da46d13e294546395a5.tar.bz2 llvm-1b290a139ad707585ecb3da46d13e294546395a5.tar.xz | |
Expand and rewrite comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189998 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/swift-vldm.ll | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/test/CodeGen/ARM/swift-vldm.ll b/test/CodeGen/ARM/swift-vldm.ll index 582a04066f..67ae00ad7d 100644 --- a/test/CodeGen/ARM/swift-vldm.ll +++ b/test/CodeGen/ARM/swift-vldm.ll @@ -1,7 +1,8 @@ ; RUN: llc < %s -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s -; vldm with registers not aligned with q registers need more micro-ops so that -; so that there usage becomes unbeneficial on swift. +; Check that we avoid producing vldm instructions using d registers that +; begin in the most-significant half of a q register. These require more +; micro-ops on swift and so aren't worth combining. ; CHECK-LABEL: test_vldm ; CHECK: vldmia r{{[0-9]+}}, {d2, d3, d4} @@ -19,7 +20,7 @@ entry: %d2 = load double * %addr1 %d3 = load double * %addr2 %d4 = load double * %addr3 - ; We are trying to force x[0-3] in register d1 to d4 so that we can test we + ; We are trying to force x[0-3] in registers d1 to d4 so that we can test we ; don't form a "vldmia rX, {d1, d2, d3, d4}". ; We are relying on the calling convention and that register allocation ; properly coalesces registers. |