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| author | Silviu Baranga <silviu.baranga@arm.com> | 2012-04-05 16:19:29 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-04-05 16:19:29 +0000 |
| commit | 1c01249191ba5d3648e7bedaf8233c41cc103551 (patch) | |
| tree | d1ccb1b1271b6d4b01c63eef2549bb96110b222e /test | |
| parent | 82e1bba0e4afaf3769fc46819c1601e387ffb56e (diff) | |
| download | llvm-1c01249191ba5d3648e7bedaf8233c41cc103551.tar.gz llvm-1c01249191ba5d3648e7bedaf8233c41cc103551.tar.bz2 llvm-1c01249191ba5d3648e7bedaf8233c41cc103551.tar.xz | |
Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154101 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt new file mode 100644 index 0000000000..275bae2fa2 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x1f 0x12 0xb0 0x00 +0x1f 0x12 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0xf2 0xb0 0x00 +0x13 0xf2 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0x1f 0xb0 0x00 +0x13 0x1f 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0x12 0xbf 0x00 +0x13 0x12 0xbf 0x00 |