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| author | Andrew Trick <atrick@apple.com> | 2012-06-13 02:39:03 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-06-13 02:39:03 +0000 |
| commit | 1c2d3c538c6062655f2b37438cc69a769ab90942 (patch) | |
| tree | eb0b328855aaf54e6d864d89621e73212be3f84a /test | |
| parent | 9df55eed0470c898c4003dc433c4479bdb0e0aac (diff) | |
| download | llvm-1c2d3c538c6062655f2b37438cc69a769ab90942.tar.gz llvm-1c2d3c538c6062655f2b37438cc69a769ab90942.tar.bz2 llvm-1c2d3c538c6062655f2b37438cc69a769ab90942.tar.xz | |
sched: fix latency of memory dependence chain edges for consistency.
For store->load dependencies that may alias, we should always use
TrueMemOrderLatency, which may eventually become a subtarget hook. In
effect, we should guarantee at least TrueMemOrderLatency on at least
one DAG path from a store to a may-alias load.
This should fix the standard mode as well as -enable-aa-sched-mi".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158380 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll new file mode 100644 index 0000000000..b05ec6367e --- /dev/null +++ b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -o /dev/null "-mtriple=thumbv7-apple-ios" -debug-only=post-RA-sched 2> %t +; RUN: FileCheck %s < %t +; REQUIRES: asserts +; Make sure that mayalias store-load dependencies have one cycle +; latency regardless of whether they are barriers or not. + +; CHECK: ** List Scheduling +; CHECK: SU(2){{.*}}STR{{.*}}Volatile +; CHECK-NOT: ch SU +; CHECK: ch SU(3): Latency=1 +; CHECK-NOT: ch SU +; CHECK: SU(3){{.*}}LDR{{.*}}Volatile +; CHECK-NOT: ch SU +; CHECK: ch SU(2): Latency=1 +; CHECK-NOT: ch SU +; CHECK: ** List Scheduling +; CHECK: SU(2){{.*}}STR{{.*}} +; CHECK-NOT: ch SU +; CHECK: ch SU(3): Latency=1 +; CHECK-NOT: ch SU +; CHECK: SU(3){{.*}}LDR{{.*}} +; CHECK-NOT: ch SU +; CHECK: ch SU(2): Latency=1 +; CHECK-NOT: ch SU +define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind { +entry: + store volatile i32 65540, i32* %p1, align 4, !tbaa !0 + %0 = load volatile i32* %p2, align 4, !tbaa !0 + ret i32 %0 +} + +define i32 @f2(i32* nocapture %p1, i32* nocapture %p2) nounwind { +entry: + store i32 65540, i32* %p1, align 4, !tbaa !0 + %0 = load i32* %p2, align 4, !tbaa !0 + ret i32 %0 +} + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} |