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| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-09-16 12:29:33 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-09-16 12:29:33 +0000 |
| commit | 1cd1b0b283079b5a8c54759983e9e70845971b2c (patch) | |
| tree | 9e83b681f07349a3e8d5114eecde92c3fa233840 /test | |
| parent | 5754a4525625a67a6c9b4f63512ea9db6997bf05 (diff) | |
| download | llvm-1cd1b0b283079b5a8c54759983e9e70845971b2c.tar.gz llvm-1cd1b0b283079b5a8c54759983e9e70845971b2c.tar.bz2 llvm-1cd1b0b283079b5a8c54759983e9e70845971b2c.tar.xz | |
Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.
This cleans up after the mess r108567 left in the CellSPU backend.
ORCvt-instruction were used to reinterpret registers, and the ORs were then
removed by isMoveInstr(). This patch now removes 350 instrucions of format:
or $3, $3, $3
(from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is
checked for.
Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114074 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/CellSPU/v2i32.ll | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/test/CodeGen/CellSPU/v2i32.ll b/test/CodeGen/CellSPU/v2i32.ll index dd51be5a71..8cfc490e02 100644 --- a/test/CodeGen/CellSPU/v2i32.ll +++ b/test/CodeGen/CellSPU/v2i32.ll @@ -37,9 +37,8 @@ define %vec @test_mul(%vec %param) } define <2 x i32> @test_splat(i32 %param ) { -;TODO insertelement transforms to a PREFSLOT2VEC, that trasforms to the -; somewhat redundant: -;CHECK-NOT or $3, $3, $3 +;see svn log for why this is here... +;CHECK-NOT: or $3, $3, $3 ;CHECK: lqa ;CHECK: shufb %sv = insertelement <1 x i32> undef, i32 %param, i32 0 |