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| author | Tim Northover <tnorthover@apple.com> | 2014-04-18 14:54:35 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-04-18 14:54:35 +0000 |
| commit | 1d5a2ad8a63c2a45ab12fb76a7381fe5dfe187ac (patch) | |
| tree | 7f633a370626c8f31115c6cd0d9d26a20f664cbc /test | |
| parent | 936285440b8585160db4e29ff8fb8180ae728b68 (diff) | |
| download | llvm-1d5a2ad8a63c2a45ab12fb76a7381fe5dfe187ac.tar.gz llvm-1d5a2ad8a63c2a45ab12fb76a7381fe5dfe187ac.tar.bz2 llvm-1d5a2ad8a63c2a45ab12fb76a7381fe5dfe187ac.tar.xz | |
ARM64: add extra NEG pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206609 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/AArch64/neon-shl-ashr-lshr.ll | 1 | ||||
| -rw-r--r-- | test/CodeGen/ARM64/vshift.ll | 8 |
2 files changed, 9 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/neon-shl-ashr-lshr.ll b/test/CodeGen/AArch64/neon-shl-ashr-lshr.ll index 0b520d7ac8..628a6760c9 100644 --- a/test/CodeGen/AArch64/neon-shl-ashr-lshr.ll +++ b/test/CodeGen/AArch64/neon-shl-ashr-lshr.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s +; arm64 has all tests not involving v1iN. define <8 x i8> @shl.v8i8(<8 x i8> %a, <8 x i8> %b) { ; CHECK-LABEL: shl.v8i8: diff --git a/test/CodeGen/ARM64/vshift.ll b/test/CodeGen/ARM64/vshift.ll index ae5da38a22..486c6cc390 100644 --- a/test/CodeGen/ARM64/vshift.ll +++ b/test/CodeGen/ARM64/vshift.ll @@ -1907,3 +1907,11 @@ declare <16 x i8> @llvm.arm64.neon.vsli.v16i8(<16 x i8>, <16 x i8>, i32) nounwin declare <8 x i16> @llvm.arm64.neon.vsli.v8i16(<8 x i16>, <8 x i16>, i32) nounwind readnone declare <4 x i32> @llvm.arm64.neon.vsli.v4i32(<4 x i32>, <4 x i32>, i32) nounwind readnone declare <2 x i64> @llvm.arm64.neon.vsli.v2i64(<2 x i64>, <2 x i64>, i32) nounwind readnone + +define <1 x i64> @ashr_v1i64(<1 x i64> %a, <1 x i64> %b) { +; CHECK-LABEL: ashr_v1i64: +; CHECK: neg d{{[0-9]+}}, d{{[0-9]+}} +; CHECK: sshl d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} + %c = ashr <1 x i64> %a, %b + ret <1 x i64> %c +} |