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| author | Lang Hames <lhames@gmail.com> | 2013-10-21 17:51:24 +0000 |
|---|---|---|
| committer | Lang Hames <lhames@gmail.com> | 2013-10-21 17:51:24 +0000 |
| commit | 1d82537762a0f4019bde301d498d190140585f57 (patch) | |
| tree | 85024ec02b3891da0b68ca933c8b5a251534c394 /test | |
| parent | ef2d919f7f767b9d70bc44c4ac918b0a6b540cac (diff) | |
| download | llvm-1d82537762a0f4019bde301d498d190140585f57.tar.gz llvm-1d82537762a0f4019bde301d498d190140585f57.tar.bz2 llvm-1d82537762a0f4019bde301d498d190140585f57.tar.xz | |
X86 vector element shift-by-immediate instructions take i8 immediates. Make
the instruction defenitions and ISEL reflect this.
Prior to this patch these instructions took an i32i8imm, and the high bits were
dropped during encoding. This led to incorrect behavior for shifts by
immediates higher than 255. This patch fixes that issue by detecting large
immediate shifts and returning constant zero (for logical shifts) or capping
the shift amount at an encodable value (for arithmetic shifts).
Fixes <rdar://problem/14968098>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193096 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/X86/avx2-vector-shifts.ll | 4 | ||||
| -rw-r--r-- | test/CodeGen/X86/sse2-vector-shifts.ll | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/X86/avx2-vector-shifts.ll b/test/CodeGen/X86/avx2-vector-shifts.ll index a978d93fc5..5592e6c8a5 100644 --- a/test/CodeGen/X86/avx2-vector-shifts.ll +++ b/test/CodeGen/X86/avx2-vector-shifts.ll @@ -121,7 +121,7 @@ entry: } ; CHECK-LABEL: test_sraw_3: -; CHECK: vpsraw $16, %ymm0, %ymm0 +; CHECK: vpsraw $15, %ymm0, %ymm0 ; CHECK: ret define <8 x i32> @test_srad_1(<8 x i32> %InVec) { @@ -151,7 +151,7 @@ entry: } ; CHECK-LABEL: test_srad_3: -; CHECK: vpsrad $32, %ymm0, %ymm0 +; CHECK: vpsrad $31, %ymm0, %ymm0 ; CHECK: ret ; SSE Logical Shift Right diff --git a/test/CodeGen/X86/sse2-vector-shifts.ll b/test/CodeGen/X86/sse2-vector-shifts.ll index e2d612567a..462def980a 100644 --- a/test/CodeGen/X86/sse2-vector-shifts.ll +++ b/test/CodeGen/X86/sse2-vector-shifts.ll @@ -121,7 +121,7 @@ entry: } ; CHECK-LABEL: test_sraw_3: -; CHECK: psraw $16, %xmm0 +; CHECK: psraw $15, %xmm0 ; CHECK-NEXT: ret define <4 x i32> @test_srad_1(<4 x i32> %InVec) { @@ -151,7 +151,7 @@ entry: } ; CHECK-LABEL: test_srad_3: -; CHECK: psrad $32, %xmm0 +; CHECK: psrad $31, %xmm0 ; CHECK-NEXT: ret ; SSE Logical Shift Right |