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| author | Quentin Colombet <qcolombet@apple.com> | 2013-09-17 00:26:56 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2013-09-17 00:26:56 +0000 |
| commit | 24e1b39a24ca7b8866a636498173f3959b561058 (patch) | |
| tree | f20894f519fc3958c81366354c11ee059f984724 /test | |
| parent | 06b005f17a110396f95dfbabfa988aa94d195f9a (diff) | |
| download | llvm-24e1b39a24ca7b8866a636498173f3959b561058.tar.gz llvm-24e1b39a24ca7b8866a636498173f3959b561058.tar.bz2 llvm-24e1b39a24ca7b8866a636498173f3959b561058.tar.xz | |
[SelectionDAG] Teach the vector scalarizer about TRUNCATE.
When a truncate node defines a legal vector type but uses an illegal
vector type, the legalization process was splitting the vector until
<1 x vector> type, but then it was failing to scalarize the node because
it did not know how to handle TRUNCATE.
<rdar://problem/14989896>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190830 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/vector-DAGCombine.ll | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/vector-DAGCombine.ll b/test/CodeGen/ARM/vector-DAGCombine.ll index 4221c98424..793934e746 100644 --- a/test/CodeGen/ARM/vector-DAGCombine.ll +++ b/test/CodeGen/ARM/vector-DAGCombine.ll @@ -224,3 +224,23 @@ entry: %vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %1) ret <8 x i16> %vmull.i } + +; <rdar://problem/14989896> Make sure we manage to truncate a vector from an +; illegal type to a legal type. +define <2 x i8> @test_truncate(<2 x i128> %in) { +; CHECK-LABEL: test_truncate: +; CHECK: mov [[BASE:r[0-9]+]], sp +; CHECK-NEXT: vld1.32 {[[REG1:d[0-9]+]][0]}, {{\[}}[[BASE]]:32] +; CHECK-NEXT: add [[BASE2:r[0-9]+]], [[BASE]], #4 +; CHECK-NEXT: vld1.32 {[[REG1]][1]}, {{\[}}[[BASE2]]:32] +; REG2 Should map on the same Q register as REG1, i.e., REG2 = REG1 - 1, but we +; cannot express that. +; CHECK-NEXT: vmov.32 [[REG2:d[0-9]+]][0], r0 +; CHECK-NEXT: vmov.32 [[REG2]][1], r1 +; The Q register used here should match floor(REG1/2), but we cannot express that. +; CHECK-NEXT: vmovn.i64 [[RES:d[0-9]+]], q{{[0-9]+}} +; CHECK-NEXT: vmov r0, r1, [[RES]] +entry: + %res = trunc <2 x i128> %in to <2 x i8> + ret <2 x i8> %res +} |