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author | Jiangning Liu <jiangning.liu@arm.com> | 2013-11-06 02:25:49 +0000 |
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committer | Jiangning Liu <jiangning.liu@arm.com> | 2013-11-06 02:25:49 +0000 |
commit | 258115258f8fe15e9d74b5fb524f90b75bb917d1 (patch) | |
tree | f7df585491dc8c3376135fb0e8d39db4dd0b643a /test | |
parent | 10bb82e54fc0608e6220581bda0405af8f12d32f (diff) | |
download | llvm-258115258f8fe15e9d74b5fb524f90b75bb917d1.tar.gz llvm-258115258f8fe15e9d74b5fb524f90b75bb917d1.tar.bz2 llvm-258115258f8fe15e9d74b5fb524f90b75bb917d1.tar.xz |
Implement AArch64 Neon instruction set Bitwise Extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/AArch64/neon-extract.ll | 190 | ||||
-rw-r--r-- | test/MC/AArch64/neon-diagnostics.s | 41 | ||||
-rw-r--r-- | test/MC/AArch64/neon-extract.s | 13 | ||||
-rw-r--r-- | test/MC/Disassembler/AArch64/neon-instructions.txt | 9 |
4 files changed, 253 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/neon-extract.ll b/test/CodeGen/AArch64/neon-extract.ll new file mode 100644 index 0000000000..5c52cd3067 --- /dev/null +++ b/test/CodeGen/AArch64/neon-extract.ll @@ -0,0 +1,190 @@ +; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s + +define <8 x i8> @test_vext_s8(<8 x i8> %a, <8 x i8> %b) { +; CHECK: test_vext_s8: +; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x2 +entry: + %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9> + ret <8 x i8> %vext +} + +define <4 x i16> @test_vext_s16(<4 x i16> %a, <4 x i16> %b) { +; CHECK: test_vext_s16: +; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x6 +entry: + %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6> + ret <4 x i16> %vext +} + +define <2 x i32> @test_vext_s32(<2 x i32> %a, <2 x i32> %b) { +; CHECK: test_vext_s32: +; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x4 +entry: + %vext = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 2> + ret <2 x i32> %vext +} + +define <1 x i64> @test_vext_s64(<1 x i64> %a, <1 x i64> %b) { +; CHECK: test_vext_s64: +entry: + %vext = shufflevector <1 x i64> %a, <1 x i64> %b, <1 x i32> <i32 0> + ret <1 x i64> %vext +} + +define <16 x i8> @test_vextq_s8(<16 x i8> %a, <16 x i8> %b) { +; CHECK: test_vextq_s8: +; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x2 +entry: + %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17> + ret <16 x i8> %vext +} + +define <8 x i16> @test_vextq_s16(<8 x i16> %a, <8 x i16> %b) { +; CHECK: test_vextq_s16: +; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x6 +entry: + %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> + ret <8 x i16> %vext +} + +define <4 x i32> @test_vextq_s32(<4 x i32> %a, <4 x i32> %b) { +; CHECK: test_vextq_s32: +; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x4 +entry: + %vext = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4> + ret <4 x i32> %vext +} + +define <2 x i64> @test_vextq_s64(<2 x i64> %a, <2 x i64> %b) { +; CHECK: test_vextq_s64: +; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x8 +entry: + %vext = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2> + ret <2 x i64> %vext +} + +define <8 x i8> @test_vext_u8(<8 x i8> %a, <8 x i8> %b) { +; CHECK: test_vext_u8: +; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x2 +entry: + %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9> + ret <8 x i8> %vext +} + +define <4 x i16> @test_vext_u16(<4 x i16> %a, <4 x i16> %b) { +; CHECK: test_vext_u16: +; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x6 +entry: + %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6> + ret <4 x i16> %vext +} + +define <2 x i32> @test_vext_u32(<2 x i32> %a, <2 x i32> %b) { +; CHECK: test_vext_u32: +; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x4 +entry: + %vext = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 2> + ret <2 x i32> %vext +} + +define <1 x i64> @test_vext_u64(<1 x i64> %a, <1 x i64> %b) { +; CHECK: test_vext_u64: +entry: + %vext = shufflevector <1 x i64> %a, <1 x i64> %b, <1 x i32> <i32 0> + ret <1 x i64> %vext +} + +define <16 x i8> @test_vextq_u8(<16 x i8> %a, <16 x i8> %b) { +; CHECK: test_vextq_u8: +; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x2 +entry: + %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17> + ret <16 x i8> %vext +} + +define <8 x i16> @test_vextq_u16(<8 x i16> %a, <8 x i16> %b) { +; CHECK: test_vextq_u16: +; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x6 +entry: + %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> + ret <8 x i16> %vext +} + +define <4 x i32> @test_vextq_u32(<4 x i32> %a, <4 x i32> %b) { +; CHECK: test_vextq_u32: +; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x4 +entry: + %vext = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4> + ret <4 x i32> %vext +} + +define <2 x i64> @test_vextq_u64(<2 x i64> %a, <2 x i64> %b) { +; CHECK: test_vextq_u64: +; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x8 +entry: + %vext = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2> + ret <2 x i64> %vext +} + +define <2 x float> @test_vext_f32(<2 x float> %a, <2 x float> %b) { +; CHECK: test_vext_f32: +; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x4 +entry: + %vext = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 2> + ret <2 x float> %vext +} + +define <1 x double> @test_vext_f64(<1 x double> %a, <1 x double> %b) { +; CHECK: test_vext_f64: +entry: + %vext = shufflevector <1 x double> %a, <1 x double> %b, <1 x i32> <i32 0> + ret <1 x double> %vext +} + +define <4 x float> @test_vextq_f32(<4 x float> %a, <4 x float> %b) { +; CHECK: test_vextq_f32: +; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x4 +entry: + %vext = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4> + ret <4 x float> %vext +} + +define <2 x double> @test_vextq_f64(<2 x double> %a, <2 x double> %b) { +; CHECK: test_vextq_f64: +; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x8 +entry: + %vext = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2> + ret <2 x double> %vext +} + +define <8 x i8> @test_vext_p8(<8 x i8> %a, <8 x i8> %b) { +; CHECK: test_vext_p8: +; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x2 +entry: + %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9> + ret <8 x i8> %vext +} + +define <4 x i16> @test_vext_p16(<4 x i16> %a, <4 x i16> %b) { +; CHECK: test_vext_p16: +; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x6 +entry: + %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6> + ret <4 x i16> %vext +} + +define <16 x i8> @test_vextq_p8(<16 x i8> %a, <16 x i8> %b) { +; CHECK: test_vextq_p8: +; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x2 +entry: + %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17> + ret <16 x i8> %vext +} + +define <8 x i16> @test_vextq_p16(<8 x i16> %a, <8 x i16> %b) { +; CHECK: test_vextq_p16: +; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x6 +entry: + %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> + ret <8 x i16> %vext +} diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s index 67a938ed77..b549480a8f 100644 --- a/test/MC/AArch64/neon-diagnostics.s +++ b/test/MC/AArch64/neon-diagnostics.s @@ -5194,3 +5194,44 @@ // CHECK: error: invalid operand for instruction // CHECK: sha256su1 v0.16b, v1.16b, v2.16b // CHECK: ^ + +//---------------------------------------------------------------------- +// Bitwise extract +//---------------------------------------------------------------------- + + ext v0.8b, v1.8b, v2.4h, #0x3 + ext v0.4h, v1.4h, v2.4h, #0x3 + ext v0.2s, v1.2s, v2.2s, #0x1 + ext v0.1d, v1.1d, v2.1d, #0x0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.8b, v1.8b, v2.4h, #0x3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.4h, v1.4h, v2.4h, #0x3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.2s, v1.2s, v2.2s, #0x1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.1d, v1.1d, v2.1d, #0x0 +// CHECK-ERROR: ^ + + ext v0.16b, v1.16b, v2.8h, #0x3 + ext v0.8h, v1.8h, v2.8h, #0x3 + ext v0.4s, v1.4s, v2.4s, #0x1 + ext v0.2d, v1.2d, v2.2d, #0x0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.16b, v1.16b, v2.8h, #0x3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.8h, v1.8h, v2.8h, #0x3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.4s, v1.4s, v2.4s, #0x1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.2d, v1.2d, v2.2d, #0x0 +// CHECK-ERROR: ^ + diff --git a/test/MC/AArch64/neon-extract.s b/test/MC/AArch64/neon-extract.s new file mode 100644 index 0000000000..2d58a75a49 --- /dev/null +++ b/test/MC/AArch64/neon-extract.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Instructions for bitwise extract +//------------------------------------------------------------------------------ + + ext v0.8b, v1.8b, v2.8b, #0x3 + ext v0.16b, v1.16b, v2.16b, #0x3 + +// CHECK: ext v0.8b, v1.8b, v2.8b, #0x3 // encoding: [0x20,0x18,0x02,0x2e] +// CHECK: ext v0.16b, v1.16b, v2.16b, #0x3 // encoding: [0x20,0x18,0x02,0x6e] diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt index c320d7da09..225bb16212 100644 --- a/test/MC/Disassembler/AArch64/neon-instructions.txt +++ b/test/MC/Disassembler/AArch64/neon-instructions.txt @@ -2042,3 +2042,12 @@ G# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | 0x00,0x80,0x81,0x4c 0xef,0x45,0x82,0x4c 0xff,0x0b,0x9f,0x4c + +#---------------------------------------------------------------------- +# Bitwise extract +#---------------------------------------------------------------------- +0x20,0x18,0x02,0x2e +0x20,0x18,0x02,0x6e +# CHECK: ext v0.8b, v1.8b, v2.8b, #0x3 +# CHECK: ext v0.16b, v1.16b, v2.16b, #0x3 + |