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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2012-10-10 21:25:01 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2012-10-10 21:25:01 +0000 |
| commit | 26160f4e6403f3ddd7c4599422578cb46777103d (patch) | |
| tree | 932119198bde25a7908b03c96ca07b03a12b427f /test | |
| parent | a5d0ab555384baa293b06686bec5a01fb9638ca3 (diff) | |
| download | llvm-26160f4e6403f3ddd7c4599422578cb46777103d.tar.gz llvm-26160f4e6403f3ddd7c4599422578cb46777103d.tar.bz2 llvm-26160f4e6403f3ddd7c4599422578cb46777103d.tar.xz | |
When generating spill and reload code for vector registers on PowerPC,
the compiler makes use of GPR0. However, there are two flavors of
GPR0 defined by the target: the 32-bit GPR0 (R0) and the 64-bit GPR0
(X0). The spill/reload code makes use of R0 regardless of whether we
are generating 32- or 64-bit code.
This patch corrects the problem in the obvious manner, using X0 and
ADDI8 for 64-bit and R0 and ADDI for 32-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165658 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/PowerPC/vrspill.ll | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/vrspill.ll b/test/CodeGen/PowerPC/vrspill.ll new file mode 100644 index 0000000000..fdd200c103 --- /dev/null +++ b/test/CodeGen/PowerPC/vrspill.ll @@ -0,0 +1,19 @@ +; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s + +; This verifies that we generate correct spill/reload code for vector regs. + +define void @addrtaken(i32 %i, <4 x float> %w) nounwind { +entry: + %i.addr = alloca i32, align 4 + %w.addr = alloca <4 x float>, align 16 + store i32 %i, i32* %i.addr, align 4 + store <4 x float> %w, <4 x float>* %w.addr, align 16 + call void @foo(i32* %i.addr) + ret void +} + +; CHECK: stvx 2, 0, 0 +; CHECK: lvx 2, 0, 0 + +declare void @foo(i32*) |