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authorJakob Stoklund Olesen <stoklund@2pi.dk>2012-08-15 22:16:39 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2012-08-15 22:16:39 +0000
commit2860b7ea3a1d60213ee7228bd274bc4f8b170772 (patch)
treeb01f0e59fa7da8121848824f06495d6a0509f57c /test
parent8dd2e5bf8331f55e099763bab2b95f7509649b84 (diff)
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Fold predicable instructions into MOVCC / t2MOVCC.
The ARM select instructions are just predicated moves. If the select is the only use of an operand, the instruction defining the operand can be predicated instead, saving one instruction and decreasing register pressure. This implementation can turn AND/ORR/EOR instructions into their corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to predicate any instruction, but we don't yet support predicated instructions in SSA form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161994 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/ARM/select_xform.ll60
-rw-r--r--test/CodeGen/Thumb2/machine-licm.ll2
2 files changed, 61 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/select_xform.ll b/test/CodeGen/ARM/select_xform.ll
index ca2e18a639..d98d7a628e 100644
--- a/test/CodeGen/ARM/select_xform.ll
+++ b/test/CodeGen/ARM/select_xform.ll
@@ -104,3 +104,63 @@ entry:
ret i32 %tmp3
}
+; Fold ORRri into movcc.
+define i32 @t8(i32 %a, i32 %b) nounwind {
+; ARM: t8:
+; ARM: cmp r0, r1
+; ARM: orrge r0, r1, #1
+
+; T2: t8:
+; T2: cmp r0, r1
+; T2: orrge r0, r1, #1
+ %x = or i32 %b, 1
+ %cond = icmp slt i32 %a, %b
+ %tmp1 = select i1 %cond, i32 %a, i32 %x
+ ret i32 %tmp1
+}
+
+; Fold ANDrr into movcc.
+define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind {
+; ARM: t9:
+; ARM: cmp r0, r1
+; ARM: andge r0, r1, r2
+
+; T2: t9:
+; T2: cmp r0, r1
+; T2: andge.w r0, r1, r2
+ %x = and i32 %b, %c
+ %cond = icmp slt i32 %a, %b
+ %tmp1 = select i1 %cond, i32 %a, i32 %x
+ ret i32 %tmp1
+}
+
+; Fold EORrs into movcc.
+define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
+; ARM: t10:
+; ARM: cmp r0, r1
+; ARM: eorge r0, r1, r2, lsl #7
+
+; T2: t10:
+; T2: cmp r0, r1
+; T2: eorge.w r0, r1, r2, lsl #7
+ %s = shl i32 %c, 7
+ %x = xor i32 %b, %s
+ %cond = icmp slt i32 %a, %b
+ %tmp1 = select i1 %cond, i32 %a, i32 %x
+ ret i32 %tmp1
+}
+
+; Fold ORRri into movcc, reversing the condition.
+define i32 @t11(i32 %a, i32 %b) nounwind {
+; ARM: t11:
+; ARM: cmp r0, r1
+; ARM: orrlt r0, r1, #1
+
+; T2: t11:
+; T2: cmp r0, r1
+; T2: orrlt r0, r1, #1
+ %x = or i32 %b, 1
+ %cond = icmp slt i32 %a, %b
+ %tmp1 = select i1 %cond, i32 %x, i32 %a
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll
index 82857425a9..01df373232 100644
--- a/test/CodeGen/Thumb2/machine-licm.ll
+++ b/test/CodeGen/Thumb2/machine-licm.ll
@@ -95,7 +95,7 @@ bb.nph:
bb: ; preds = %bb, %bb.nph
; CHECK: bb
; CHECK: eor.w
-; CHECK: eor.w {{(r[0-9])|(lr)}}, {{(r[0-9])|(lr)}}, [[REGISTER]]
+; CHECK: eorne.w {{(r[0-9])|(lr)}}, {{(r[0-9])|(lr)}}, [[REGISTER]]
; CHECK-NOT: eor
; CHECK: and
%data_addr.013 = phi i8 [ %data, %bb.nph ], [ %8, %bb ] ; <i8> [#uses=2]