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| author | Kristof Beyls <kristof.beyls@arm.com> | 2013-02-22 10:01:33 +0000 |
|---|---|---|
| committer | Kristof Beyls <kristof.beyls@arm.com> | 2013-02-22 10:01:33 +0000 |
| commit | 29e05fe7a885bd03d8570d2bcf14193013776bcd (patch) | |
| tree | 34a8c2abf3930ebe1e31f1f839a886628f51a9e9 /test | |
| parent | 351b7a10e2560a835759748c58da09e53207b39d (diff) | |
| download | llvm-29e05fe7a885bd03d8570d2bcf14193013776bcd.tar.gz llvm-29e05fe7a885bd03d8570d2bcf14193013776bcd.tar.bz2 llvm-29e05fe7a885bd03d8570d2bcf14193013776bcd.tar.xz | |
Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.
The Printer will now print instructions with the correct alignment specifier syntax, like
vld1.8 {d16}, [r0:64]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
27 files changed, 407 insertions, 407 deletions
diff --git a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll index f9ede7401a..0d0d03b23e 100644 --- a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll +++ b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll @@ -8,7 +8,7 @@ define void @test_sqrt(<4 x float>* %X) nounwind { ; CHECK: movw r1, :lower16:{{.*}} ; CHECK: movt r1, :upper16:{{.*}} -; CHECK: vld1.64 {{.*}}, [r1, :128] +; CHECK: vld1.64 {{.*}}, [r1:128] ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}} ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}} ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}} @@ -252,7 +252,7 @@ define void @test_powi(<4 x float>* %X) nounwind { ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} -; CHECK: vld1.64 {{.*}}, :128 +; CHECK: vld1.64 {{.*}}:128 ; CHECK: vmul.f32 {{.*}} ; CHECK: vst1.64 diff --git a/test/CodeGen/ARM/2012-08-09-neon-extload.ll b/test/CodeGen/ARM/2012-08-09-neon-extload.ll index b55f1cae7f..764c58f2e1 100644 --- a/test/CodeGen/ARM/2012-08-09-neon-extload.ll +++ b/test/CodeGen/ARM/2012-08-09-neon-extload.ll @@ -18,7 +18,7 @@ define void @test_v2i8tov2i32() { %i32val = sext <2 x i8> %i8val to <2 x i32> store <2 x i32> %i32val, <2 x i32>* @var_v2i32 -; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :16] +; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:16] ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]] ; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}} @@ -32,7 +32,7 @@ define void @test_v2i8tov2i64() { %i64val = sext <2 x i8> %i8val to <2 x i64> store <2 x i64> %i64val, <2 x i64>* @var_v2i64 -; CHECK: vld1.16 {d{{[0-9]+}}[0]}, [{{r[0-9]+}}, :16] +; CHECK: vld1.16 {d{{[0-9]+}}[0]}, [{{r[0-9]+}}:16] ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]] ; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}} ; CHECK: vmovl.s32 {{q[0-9]+}}, {{d[0-9]+}} @@ -50,7 +50,7 @@ define void @test_v4i8tov4i16() { %i16val = sext <4 x i8> %i8val to <4 x i16> store <4 x i16> %i16val, <4 x i16>* @var_v4i16 -; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32] +; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32] ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]] ; CHECK-NOT: vmovl.s16 @@ -65,7 +65,7 @@ define void @test_v4i8tov4i32() { %i16val = sext <4 x i8> %i8val to <4 x i32> store <4 x i32> %i16val, <4 x i32>* @var_v4i32 -; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32] +; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32] ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]] ; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}} @@ -79,7 +79,7 @@ define void @test_v2i16tov2i32() { %i32val = sext <2 x i16> %i16val to <2 x i32> store <2 x i32> %i32val, <2 x i32>* @var_v2i32 -; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32] +; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32] ; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]] ; CHECK-NOT: vmovl @@ -94,7 +94,7 @@ define void @test_v2i16tov2i64() { %i64val = sext <2 x i16> %i16val to <2 x i64> store <2 x i64> %i64val, <2 x i64>* @var_v2i64 -; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32] +; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32] ; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]] ; CHECK: vmovl.s32 {{q[0-9]+}}, d[[LOAD]] diff --git a/test/CodeGen/ARM/neon_ld2.ll b/test/CodeGen/ARM/neon_ld2.ll index 497619ed74..25a670b097 100644 --- a/test/CodeGen/ARM/neon_ld2.ll +++ b/test/CodeGen/ARM/neon_ld2.ll @@ -7,10 +7,10 @@ ; CHECK: vadd.i64 q ; CHECK: vst1.64 ; SWIFT: t1 -; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}} -; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}} +; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}} +; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}} ; SWIFT: vadd.i64 q -; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}} +; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}} define void @t1(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind { entry: %0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1] @@ -28,8 +28,8 @@ entry: ; CHECK: vmov r0, r1, d ; CHECK: vmov r2, r3, d ; SWIFT: t2 -; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}} -; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}} +; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}} +; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}} ; SWIFT: vsub.i64 q ; SWIFT: vmov r0, r1, d ; SWIFT: vmov r2, r3, d diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 6d6586e4f2..fd2083cf9f 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -242,8 +242,8 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { ; CHECK: vldr ; CHECK-NOT: vmov d{{.*}}, d16 ; CHECK: vmov.i32 d17 -; CHECK-NEXT: vst1.64 {d16, d17}, [r0, :128] -; CHECK-NEXT: vst1.64 {d16, d17}, [r0, :128] +; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] +; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2] %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] store <4 x float> %4, <4 x float>* undef, align 16 diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll index 057ea11389..e93cdbc10a 100644 --- a/test/CodeGen/ARM/spill-q.ll +++ b/test/CodeGen/ARM/spill-q.ll @@ -12,8 +12,8 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly define void @aaa(%quuz* %this, i8* %block) { ; CHECK: aaa: ; CHECK: bic {{.*}}, #15 -; CHECK: vst1.64 {{.*}}sp, :128 -; CHECK: vld1.64 {{.*}}sp, :128 +; CHECK: vst1.64 {{.*}}sp:128 +; CHECK: vld1.64 {{.*}}sp:128 entry: %aligned_vec = alloca <4 x float>, align 16 %"alloca point" = bitcast i32 0 to i32 diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll index e524395c50..994f05dacb 100644 --- a/test/CodeGen/ARM/vld1.ll +++ b/test/CodeGen/ARM/vld1.ll @@ -4,7 +4,7 @@ define <8 x i8> @vld1i8(i8* %A) nounwind { ;CHECK: vld1i8: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vld1.8 {d16}, [r0, :64] +;CHECK: vld1.8 {d16}, [r0:64] %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16) ret <8 x i8> %tmp1 } @@ -68,7 +68,7 @@ define <1 x i64> @vld1i64(i64* %A) nounwind { define <16 x i8> @vld1Qi8(i8* %A) nounwind { ;CHECK: vld1Qi8: ;Check the alignment value. Max for this instruction is 128 bits: -;CHECK: vld1.8 {d16, d17}, [r0, :64] +;CHECK: vld1.8 {d16, d17}, [r0:64] %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8) ret <16 x i8> %tmp1 } @@ -76,7 +76,7 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwind { ;Check for a post-increment updating load. define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind { ;CHECK: vld1Qi8_update: -;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}, :64]! +;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]! %A = load i8** %ptr %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8) %tmp2 = getelementptr i8* %A, i32 16 @@ -87,7 +87,7 @@ define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind { define <8 x i16> @vld1Qi16(i16* %A) nounwind { ;CHECK: vld1Qi16: ;Check the alignment value. Max for this instruction is 128 bits: -;CHECK: vld1.16 {d16, d17}, [r0, :128] +;CHECK: vld1.16 {d16, d17}, [r0:128] %tmp0 = bitcast i16* %A to i8* %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0, i32 32) ret <8 x i16> %tmp1 diff --git a/test/CodeGen/ARM/vld2.ll b/test/CodeGen/ARM/vld2.ll index 29b379465d..caa016e929 100644 --- a/test/CodeGen/ARM/vld2.ll +++ b/test/CodeGen/ARM/vld2.ll @@ -14,7 +14,7 @@ define <8 x i8> @vld2i8(i8* %A) nounwind { ;CHECK: vld2i8: ;Check the alignment value. Max for this instruction is 128 bits: -;CHECK: vld2.8 {d16, d17}, [r0, :64] +;CHECK: vld2.8 {d16, d17}, [r0:64] %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 8) %tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1 @@ -25,7 +25,7 @@ define <8 x i8> @vld2i8(i8* %A) nounwind { define <4 x i16> @vld2i16(i16* %A) nounwind { ;CHECK: vld2i16: ;Check the alignment value. Max for this instruction is 128 bits: -;CHECK: vld2.16 {d16, d17}, [r0, :128] +;CHECK: vld2.16 {d16, d17}, [r0:128] %tmp0 = bitcast i16* %A to i8* %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8* %tmp0, i32 32) %tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0 @@ -74,7 +74,7 @@ define <2 x float> @vld2f_update(float** %ptr) nounwind { define <1 x i64> @vld2i64(i64* %A) nounwind { ;CHECK: vld2i64: ;Check the alignment value. Max for this instruction is 128 bits: -;CHECK: vld1.64 {d16, d17}, [r0, :128] +;CHECK: vld1.64 {d16, d17}, [r0:128] %tmp0 = bitcast i64* %A to i8* %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8* %tmp0, i32 32) %tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0 @@ -86,7 +86,7 @@ define <1 x i64> @vld2i64(i64* %A) nounwind { define <16 x i8> @vld2Qi8(i8* %A) nounwind { ;CHECK: vld2Qi8: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] +;CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64] %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 8) %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1 @@ -97,7 +97,7 @@ define <16 x i8> @vld2Qi8(i8* %A) nounwind { ;Check for a post-increment updating load with register increment. define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind { ;CHECK: vld2Qi8_update: -;CHECK: vld2.8 {d16, d17, d18, d19}, [r2, :128], r1 +;CHECK: vld2.8 {d16, d17, d18, d19}, [r2:128], r1 %A = load i8** %ptr %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 16) %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0 @@ -111,7 +111,7 @@ define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind { define <8 x i16> @vld2Qi16(i16* %A) nounwind { ;CHECK: vld2Qi16: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] +;CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128] %tmp0 = bitcast i16* %A to i8* %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8* %tmp0, i32 16) %tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0 @@ -123,7 +123,7 @@ define <8 x i16> @vld2Qi16(i16* %A) nounwind { define <4 x i32> @vld2Qi32(i32* %A) nounwind { ;CHECK: vld2Qi32: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] +;CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i32* %A to i8* %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp0, i32 64) %tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0 diff --git a/test/CodeGen/ARM/vld3.ll b/test/CodeGen/ARM/vld3.ll index b495319830..ad63e1f716 100644 --- a/test/CodeGen/ARM/vld3.ll +++ b/test/CodeGen/ARM/vld3.ll @@ -15,7 +15,7 @@ define <8 x i8> @vld3i8(i8* %A) nounwind { ;CHECK: vld3i8: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vld3.8 {d16, d17, d18}, [r0, :64] +;CHECK: vld3.8 {d16, d17, d18}, [r0:64] %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32) %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2 @@ -74,7 +74,7 @@ define <2 x float> @vld3f(float* %A) nounwind { define <1 x i64> @vld3i64(i64* %A) nounwind { ;CHECK: vld3i64: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vld1.64 {d16, d17, d18}, [r0, :64] +;CHECK: vld1.64 {d16, d17, d18}, [r0:64] %tmp0 = bitcast i64* %A to i8* %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0, i32 16) %tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0 @@ -86,8 +86,8 @@ define <1 x i64> @vld3i64(i64* %A) nounwind { define <16 x i8> @vld3Qi8(i8* %A) nounwind { ;CHECK: vld3Qi8: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! -;CHECK: vld3.8 {d17, d19, d21}, [r0, :64] +;CHECK: vld3.8 {d16, d18, d20}, [r0:64]! +;CHECK: vld3.8 {d17, d19, d21}, [r0:64] %tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8* %A, i32 32) %tmp2 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 2 diff --git a/test/CodeGen/ARM/vld4.ll b/test/CodeGen/ARM/vld4.ll index 59a73db318..9ee5fe46ee 100644 --- a/test/CodeGen/ARM/vld4.ll +++ b/test/CodeGen/ARM/vld4.ll @@ -14,7 +14,7 @@ define <8 x i8> @vld4i8(i8* %A) nounwind { ;CHECK: vld4i8: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] +;CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64] %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 8) %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2 @@ -25,7 +25,7 @@ define <8 x i8> @vld4i8(i8* %A) nounwind { ;Check for a post-increment updating load with register increment. define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind { ;CHECK: vld4i8_update: -;CHECK: vld4.8 {d16, d17, d18, d19}, [r2, :128], r1 +;CHECK: vld4.8 {d16, d17, d18, d19}, [r2:128], r1 %A = load i8** %ptr %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16) %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0 @@ -39,7 +39,7 @@ define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind { define <4 x i16> @vld4i16(i16* %A) nounwind { ;CHECK: vld4i16: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] +;CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128] %tmp0 = bitcast i16* %A to i8* %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8* %tmp0, i32 16) %tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0 @@ -51,7 +51,7 @@ define <4 x i16> @vld4i16(i16* %A) nounwind { define <2 x i32> @vld4i32(i32* %A) nounwind { ;CHECK: vld4i32: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] +;CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i32* %A to i8* %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %tmp0, i32 32) %tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0 @@ -74,7 +74,7 @@ define <2 x float> @vld4f(float* %A) nounwind { define <1 x i64> @vld4i64(i64* %A) nounwind { ;CHECK: vld4i64: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vld1.64 {d16, d17, d18, d19}, [r0, :256] +;CHECK: vld1.64 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i64* %A to i8* %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 64) %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0 @@ -86,8 +86,8 @@ define <1 x i64> @vld4i64(i64* %A) nounwind { define <16 x i8> @vld4Qi8(i8* %A) nounwind { ;CHECK: vld4Qi8: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! -;CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256] +;CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]! +;CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256] %tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8* %A, i32 64) %tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2 @@ -111,8 +111,8 @@ define <8 x i16> @vld4Qi16(i16* %A) nounwind { ;Check for a post-increment updating load. define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind { ;CHECK: vld4Qi16_update: -;CHECK: vld4.16 {d16, d18, d20, d22}, [r1, :64]! -;CHECK: vld4.16 {d17, d19, d21, d23}, [r1, :64]! +;CHECK: vld4.16 {d16, d18, d20, d22}, [r1:64]! +;CHECK: vld4.16 {d17, d19, d21, d23}, [r1:64]! %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8) diff --git a/test/CodeGen/ARM/vlddup.ll b/test/CodeGen/ARM/vlddup.ll index c69473f87f..7c7319c090 100644 --- a/test/CodeGen/ARM/vlddup.ll +++ b/test/CodeGen/ARM/vlddup.ll @@ -13,7 +13,7 @@ define <8 x i8> @vld1dupi8(i8* %A) nounwind { define <4 x i16> @vld1dupi16(i16* %A) nounwind { ;CHECK: vld1dupi16: ;Check the alignment value. Max for this instruction is 16 bits: -;CHECK: vld1.16 {d16[]}, [r0, :16] +;CHECK: vld1.16 {d16[]}, [r0:16] %tmp1 = load i16* %A, align 8 %tmp2 = insertelement <4 x i16> undef, i16 %tmp1, i32 0 %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> undef, <4 x i32> zeroinitializer @@ -23,7 +23,7 @@ define <4 x i16> @vld1dupi16(i16* %A) nounwind { define <2 x i32> @vld1dupi32(i32* %A) nounwind { ;CHECK: vld1dupi32: ;Check the alignment value. Max for this instruction is 32 bits: -;CHECK: vld1.32 {d16[]}, [r0, :32] +;CHECK: vld1.32 {d16[]}, [r0:32] %tmp1 = load i32* %A, align 8 %tmp2 = insertelement <2 x i32> undef, i32 %tmp1, i32 0 %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> undef, <2 x i32> zeroinitializer @@ -32,7 +32,7 @@ define <2 x i32> @vld1dupi32(i32* %A) nounwind { define <2 x float> @vld1dupf(float* %A) nounwind { ;CHECK: vld1dupf: -;CHECK: vld1.32 {d16[]}, [r0, :32] +;CHECK: vld1.32 {d16[]}, [r0:32] %tmp0 = load float* %A %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0 %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer @@ -51,7 +51,7 @@ define <16 x i8> @vld1dupQi8(i8* %A) nounwind { define <4 x float> @vld1dupQf(float* %A) nounwind { ;CHECK: vld1dupQf: -;CHECK: vld1.32 {d16[], d17[]}, [r0, :32] +;CHECK: vld1.32 {d16[], d17[]}, [r0:32] %tmp0 = load float* %A %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer @@ -109,7 +109,7 @@ define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind { define <2 x i32> @vld2dupi32(i8* %A) nounwind { ;CHECK: vld2dupi32: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vld2.32 {d16[], d17[]}, [r0, :64] +;CHECK: vld2.32 {d16[], d17[]}, [r0:64] %tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16) %tmp1 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 0 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer @@ -194,7 +194,7 @@ define <2 x i32> @vld4dupi32(i8* %A) nounwind { ;CHECK: vld4dupi32: ;Check the alignment value. An 8-byte alignment is allowed here even though ;it is smaller than the total size of the memory being loaded. -;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r0, :64] +;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r0:64] %tmp0 = tail call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %A, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 8) %tmp1 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 0 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll index 7bd0cbda02..f35fa92f5d 100644 --- a/test/CodeGen/ARM/vldlane.ll +++ b/test/CodeGen/ARM/vldlane.ll @@ -14,7 +14,7 @@ define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld1lanei16: ;Check the alignment value. Max for this instruction is 16 bits: -;CHECK: vld1.16 {d16[2]}, [r0, :16] +;CHECK: vld1.16 {d16[2]}, [r0:16] %tmp1 = load <4 x i16>* %B %tmp2 = load i16* %A, align 8 %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 2 @@ -24,7 +24,7 @@ define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld1lanei32: ;Check the alignment value. Max for this instruction is 32 bits: -;CHECK: vld1.32 {d16[1]}, [r0, :32] +;CHECK: vld1.32 {d16[1]}, [r0:32] %tmp1 = load <2 x i32>* %B %tmp2 = load i32* %A, align 8 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1 @@ -34,7 +34,7 @@ define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind { define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld1lanei32a32: ;Check the alignment value. Legal values are none or :32. -;CHECK: vld1.32 {d16[1]}, [r0, :32] +;CHECK: vld1.32 {d16[1]}, [r0:32] %tmp1 = load <2 x i32>* %B %tmp2 = load i32* %A, align 4 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1 @@ -43,7 +43,7 @@ define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind { define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vld1lanef: -;CHECK: vld1.32 {d16[1]}, [r0, :32] +;CHECK: vld1.32 {d16[1]}, [r0:32] %tmp1 = load <2 x float>* %B %tmp2 = load float* %A, align 4 %tmp3 = insertelement <2 x float> %tmp1, float %tmp2, i32 1 @@ -61,7 +61,7 @@ define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld1laneQi16: -;CHECK: vld1.16 {d17[1]}, [r0, :16] +;CHECK: vld1.16 {d17[1]}, [r0:16] %tmp1 = load <8 x i16>* %B %tmp2 = load i16* %A, align 8 %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 5 @@ -70,7 +70,7 @@ define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld1laneQi32: -;CHECK: vld1.32 {d17[1]}, [r0, :32] +;CHECK: vld1.32 {d17[1]}, [r0:32] %tmp1 = load <4 x i32>* %B %tmp2 = load i32* %A, align 8 %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 3 @@ -79,7 +79,7 @@ define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind { define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vld1laneQf: -;CHECK: vld1.32 {d16[0]}, [r0, :32] +;CHECK: vld1.32 {d16[0]}, [r0:32] %tmp1 = load <4 x float>* %B %tmp2 = load float* %A %tmp3 = insertelement <4 x float> %tmp1, float %tmp2, i32 0 @@ -98,7 +98,7 @@ define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind { define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vld2lanei8: ;Check the alignment value. Max for this instruction is 16 bits: -;CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] +;CHECK: vld2.8 {d16[1], d17[1]}, [r0:16] %tmp1 = load <8 x i8>* %B %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4) %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 @@ -110,7 +110,7 @@ define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld2lanei16: ;Check the alignment value. Max for this instruction is 32 bits: -;CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] +;CHECK: vld2.16 {d16[1], d17[1]}, [r0:32] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) @@ -176,7 +176,7 @@ define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld2laneQi32: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vld2.32 {d17[0], d19[0]}, [{{r[0-9]+}}, :64] +;CHECK: vld2.32 {d17[0], d19[0]}, [{{r[0-9]+}}:64] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16) @@ -354,7 +354,7 @@ declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8*, <4 x flo define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vld4lanei8: ;Check the alignment value. Max for this instruction is 32 bits: -;CHECK: vld4.8 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}, :32] +;CHECK: vld4.8 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}:32] %tmp1 = load <8 x i8>* %B %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 @@ -370,7 +370,7 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;Check for a post-increment updating load. define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { ;CHECK: vld4lanei8_update: -;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}, :32]! +;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:32]! %A = load i8** %ptr %tmp1 = load <8 x i8>* %B %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) @@ -408,7 +408,7 @@ define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld4lanei32: ;Check the alignment value. An 8-byte alignment is allowed here even though ;it is smaller than the total size of the memory being loaded. -;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}, :64] +;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:64] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 8) @@ -441,7 +441,7 @@ define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind { define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld4laneQi16: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [{{r[0-9]+}}, :64] +;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [{{r[0-9]+}}:64] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 16) diff --git a/test/CodeGen/ARM/vst1.ll b/test/CodeGen/ARM/vst1.ll index 364d44b711..e1f3e88907 100644 --- a/test/CodeGen/ARM/vst1.ll +++ b/test/CodeGen/ARM/vst1.ll @@ -3,7 +3,7 @@ define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst1i8: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vst1.8 {d16}, [r0, :64] +;CHECK: vst1.8 {d16}, [r0:64] %tmp1 = load <8 x i8>* %B call void @llvm.arm.neon.vst1.v8i8(i8* %A, <8 x i8> %tmp1, i32 16) ret void @@ -61,7 +61,7 @@ define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind { define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK: vst1Qi8: ;Check the alignment value. Max for this instruction is 128 bits: -;CHECK: vst1.8 {d16, d17}, [r0, :64] +;CHECK: vst1.8 {d16, d17}, [r0:64] %tmp1 = load <16 x i8>* %B call void @llvm.arm.neon.vst1.v16i8(i8* %A, <16 x i8> %tmp1, i32 8) ret void @@ -70,7 +70,7 @@ define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind { define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst1Qi16: ;Check the alignment value. Max for this instruction is 128 bits: -;CHECK: vst1.16 {d16, d17}, [r0, :128] +;CHECK: vst1.16 {d16, d17}, [r0:128] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 32) @@ -80,7 +80,7 @@ define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind { ;Check for a post-increment updating store with register increment. define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind { ;CHECK: vst1Qi16_update: -;CHECK: vst1.16 {d16, d17}, [r1, :64], r2 +;CHECK: vst1.16 {d16, d17}, [r1:64], r2 %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B diff --git a/test/CodeGen/ARM/vst2.ll b/test/CodeGen/ARM/vst2.ll index fb05a20f66..a31f8635fe 100644 --- a/test/CodeGen/ARM/vst2.ll +++ b/test/CodeGen/ARM/vst2.ll @@ -3,7 +3,7 @@ define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst2i8: ;Check the alignment value. Max for this instruction is 128 bits: -;CHECK: vst2.8 {d16, d17}, [r0, :64] +;CHECK: vst2.8 {d16, d17}, [r0:64] %tmp1 = load <8 x i8>* %B call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8) ret void @@ -24,7 +24,7 @@ define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind { define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst2i16: ;Check the alignment value. Max for this instruction is 128 bits: -;CHECK: vst2.16 {d16, d17}, [r0, :128] +;CHECK: vst2.16 {d16, d17}, [r0:128] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B call void @llvm.arm.neon.vst2.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 32) @@ -52,7 +52,7 @@ define void @vst2f(float* %A, <2 x float>* %B) nounwind { define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst2i64: ;Check the alignment value. Max for this instruction is 128 bits: -;CHECK: vst1.64 {d16, d17}, [r0, :128] +;CHECK: vst1.64 {d16, d17}, [r0:128] %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 32) @@ -62,7 +62,7 @@ define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind { ;Check for a post-increment updating store. define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind { ;CHECK: vst2i64_update: -;CHECK: vst1.64 {d16, d17}, [r1, :64]! +;CHECK: vst1.64 {d16, d17}, [r1:64]! %A = load i64** %ptr %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B @@ -75,7 +75,7 @@ define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind { define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK: vst2Qi8: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] +;CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64] %tmp1 = load <16 x i8>* %B call void @llvm.arm.neon.vst2.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 8) ret void @@ -84,7 +84,7 @@ define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind { define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst2Qi16: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] +;CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B call void @llvm.arm.neon.vst2.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 16) @@ -94,7 +94,7 @@ define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind { define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst2Qi32: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] +;CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B call void @llvm.arm.neon.vst2.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 64) diff --git a/test/CodeGen/ARM/vst3.ll b/test/CodeGen/ARM/vst3.ll index f117ab205d..281bb730fe 100644 --- a/test/CodeGen/ARM/vst3.ll +++ b/test/CodeGen/ARM/vst3.ll @@ -4,7 +4,7 @@ define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst3i8: ;Check the alignment value. Max for this instruction is 64 bits: ;This test runs at -O0 so do not check for specific register numbers. -;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64] +;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64] %tmp1 = load <8 x i8>* %B call void @llvm.arm.neon.vst3.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 32) ret void @@ -54,7 +54,7 @@ define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst3i64: ;Check the alignment value. Max for this instruction is 64 bits: ;This test runs at -O0 so do not check for specific register numbers. -;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64] +;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64] %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 16) @@ -65,8 +65,8 @@ define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK: vst3Qi8: ;Check the alignment value. Max for this instruction is 64 bits: ;This test runs at -O0 so do not check for specific register numbers. -;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64]! -;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64] +;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]! +;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64] %tmp1 = load <16 x i8>* %B call void @llvm.arm.neon.vst3.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 32) ret void diff --git a/test/CodeGen/ARM/vst4.ll b/test/CodeGen/ARM/vst4.ll index e94acb66bf..7dedb2fafe 100644 --- a/test/CodeGen/ARM/vst4.ll +++ b/test/CodeGen/ARM/vst4.ll @@ -3,7 +3,7 @@ define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst4i8: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] +;CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64] %tmp1 = load <8 x i8>* %B call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8) ret void @@ -12,7 +12,7 @@ define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind { ;Check for a post-increment updating store with register increment. define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind { ;CHECK: vst4i8_update: -;CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :128], r2 +;CHECK: vst4.8 {d16, d17, d18, d19}, [r1:128], r2 %A = load i8** %ptr %tmp1 = load <8 x i8>* %B call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 16) @@ -24,7 +24,7 @@ define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind { define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst4i16: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] +;CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B call void @llvm.arm.neon.vst4.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 16) @@ -34,7 +34,7 @@ define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind { define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst4i32: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vst4.32 {d16, d17, d18, d19}, [r0, :256] +;CHECK: vst4.32 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B call void @llvm.arm.neon.vst4.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 32) @@ -53,7 +53,7 @@ define void @vst4f(float* %A, <2 x float>* %B) nounwind { define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst4i64: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vst1.64 {d16, d17, d18, d19}, [r0, :256] +;CHECK: vst1.64 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B call void @llvm.arm.neon.vst4.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 64) @@ -63,8 +63,8 @@ define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind { define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK: vst4Qi8: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! -;CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256] +;CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]! +;CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256] %tmp1 = load <16 x i8>* %B call void @llvm.arm.neon.vst4.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 64) ret void diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll index 758b355736..67f251f706 100644 --- a/test/CodeGen/ARM/vstlane.ll +++ b/test/CodeGen/ARM/vstlane.ll @@ -26,7 +26,7 @@ define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst1lanei16: ;Check the alignment value. Max for this instruction is 16 bits: -;CHECK: vst1.16 {d16[2]}, [r0, :16] +;CHECK: vst1.16 {d16[2]}, [r0:16] %tmp1 = load <4 x i16>* %B %tmp2 = extractelement <4 x i16> %tmp1, i32 2 store i16 %tmp2, i16* %A, align 8 @@ -36,7 +36,7 @@ define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind { define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst1lanei32: ;Check the alignment value. Max for this instruction is 32 bits: -;CHECK: vst1.32 {d16[1]}, [r0, :32] +;CHECK: vst1.32 {d16[1]}, [r0:32] %tmp1 = load <2 x i32>* %B %tmp2 = extractelement <2 x i32> %tmp1, i32 1 store i32 %tmp2, i32* %A, align 8 @@ -45,7 +45,7 @@ define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind { define void @vst1lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst1lanef: -;CHECK: vst1.32 {d16[1]}, [r0, :32] +;CHECK: vst1.32 {d16[1]}, [r0:32] %tmp1 = load <2 x float>* %B %tmp2 = extractelement <2 x float> %tmp1, i32 1 store float %tmp2, float* %A @@ -64,7 +64,7 @@ define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind { define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst1laneQi16: -;CHECK: vst1.16 {d17[1]}, [r0, :16] +;CHECK: vst1.16 {d17[1]}, [r0:16] %tmp1 = load <8 x i16>* %B %tmp2 = extractelement <8 x i16> %tmp1, i32 5 store i16 %tmp2, i16* %A, align 8 @@ -74,7 +74,7 @@ define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind { define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst1laneQi32: ; // Can use scalar load. No need to use vectors. -; // CHE-CK: vst1.32 {d17[1]}, [r0, :32] +; // CHE-CK: vst1.32 {d17[1]}, [r0:32] %tmp1 = load <4 x i32>* %B %tmp2 = extractelement <4 x i32> %tmp1, i32 3 store i32 %tmp2, i32* %A, align 8 @@ -85,7 +85,7 @@ define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind { define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { ;CHECK: vst1laneQi32_update: ; // Can use scalar load. No need to use vectors. -; // CHE-CK: vst1.32 {d17[1]}, [r1, :32]! +; // CHE-CK: vst1.32 {d17[1]}, [r1:32]! %A = load i32** %ptr %tmp1 = load <4 x i32>* %B %tmp2 = extractelement <4 x i32> %tmp1, i32 3 @@ -108,7 +108,7 @@ define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind { define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst2lanei8: ;Check the alignment value. Max for this instruction is 16 bits: -;CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] +;CHECK: vst2.8 {d16[1], d17[1]}, [r0:16] %tmp1 = load <8 x i8>* %B call void @llvm.arm.neon.vst2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4) ret void @@ -117,7 +117,7 @@ define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind { define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst2lanei16: ;Check the alignment value. Max for this instruction is 32 bits: -;CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] +;CHECK: vst2.16 {d16[1], d17[1]}, [r0:32] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) @@ -168,7 +168,7 @@ define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind { define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst2laneQi32: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] +;CHECK: vst2.32 {d17[0], d19[0]}, [r0:64] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B call void @llvm.arm.neon.vst2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16) @@ -283,7 +283,7 @@ declare void @llvm.arm.neon.vst3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x f define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst4lanei8: ;Check the alignment value. Max for this instruction is 32 bits: -;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] %tmp1 = load <8 x i8>* %B call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) ret void @@ -292,7 +292,7 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;Check for a post-increment updating store. define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { ;CHECK: vst4lanei8_update: -;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]! +;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]! %A = load i8** %ptr %tmp1 = load <8 x i8>* %B call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) @@ -313,7 +313,7 @@ define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind { define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst4lanei32: ;Check the alignment value. Max for this instruction is 128 bits: -;CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +;CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B call void @llvm.arm.neon.vst4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 16) @@ -332,7 +332,7 @@ define void @vst4lanef(float* %A, <2 x float>* %B) nounwind { define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst4laneQi16: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] +;CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B call void @llvm.arm.neon.vst4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7, i32 16) diff --git a/test/CodeGen/Thumb2/aligned-spill.ll b/test/CodeGen/Thumb2/aligned-spill.ll index c98ca80985..3a2803f91f 100644 --- a/test/CodeGen/Thumb2/aligned-spill.ll +++ b/test/CodeGen/Thumb2/aligned-spill.ll @@ -26,8 +26,8 @@ entry: ; NEON: bic r4, r4, #15 ; Stack pointer must be updated before the spills. ; NEON: mov sp, r4 -; NEON: vst1.64 {d8, d9, d10, d11}, [r4, :128]! -; NEON: vst1.64 {d12, d13, d14, d15}, [r4, :128] +; NEON: vst1.64 {d8, d9, d10, d11}, [r4:128]! +; NEON: vst1.64 {d12, d13, d14, d15}, [r4:128] ; Stack pointer adjustment for the stack frame contents. ; This could legally happen before the spills. ; Since the spill slot is only 8 bytes, technically it would be fine to only @@ -36,8 +36,8 @@ entry: ; NEON: sub sp, #16 ; The epilog is free to use another scratch register than r4. ; NEON: add r[[R4:[0-9]+]], sp, #16 -; NEON: vld1.64 {d8, d9, d10, d11}, [r[[R4]], :128]! -; NEON: vld1.64 {d12, d13, d14, d15}, [r[[R4]], :128] +; NEON: vld1.64 {d8, d9, d10, d11}, [r[[R4]]:128]! +; NEON: vld1.64 {d12, d13, d14, d15}, [r[[R4]]:128] ; The stack pointer restore must happen after the reloads. ; NEON: mov sp, ; NEON: pop @@ -57,8 +57,8 @@ entry: ; NEON: bic r4, r4, #15 ; Stack pointer must be updated before the spills. ; NEON: mov sp, r4 -; NEON: vst1.64 {d8, d9, d10, d11}, [r4, :128]! -; NEON: vst1.64 {d12, d13}, [r4, :128] +; NEON: vst1.64 {d8, d9, d10, d11}, [r4:128]! +; NEON: vst1.64 {d12, d13}, [r4:128] ; NEON: vstr d14, [r4, #16] ; Epilog ; NEON: vld1.64 {d8, d9, d10, d11}, @@ -84,7 +84,7 @@ entry: ; NEON: bic r4, r4, #15 ; Stack pointer must be updated before the spills. ; NEON: mov sp, r4 -; NEON: vst1.64 {d8, d9}, [r4, :128] +; NEON: vst1.64 {d8, d9}, [r4:128] ; NEON: vstr d10, [r4, #16] ; Epilog ; NEON: vld1.64 {d8, d9}, diff --git a/test/CodeGen/Thumb2/thumb2-spill-q.ll b/test/CodeGen/Thumb2/thumb2-spill-q.ll index d9a0617f5a..5bff268e2c 100644 --- a/test/CodeGen/Thumb2/thumb2-spill-q.ll +++ b/test/CodeGen/Thumb2/thumb2-spill-q.ll @@ -12,8 +12,8 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly define void @aaa(%quuz* %this, i8* %block) { ; CHECK: aaa: ; CHECK: bic r4, r4, #15 -; CHECK: vst1.64 {{.*}}[{{.*}}, :128] -; CHECK: vld1.64 {{.*}}[{{.*}}, :128] +; CHECK: vst1.64 {{.*}}[{{.*}}:128] +; CHECK: vld1.64 {{.*}}[{{.*}}:128] entry: %aligned_vec = alloca <4 x float>, align 16 %"alloca point" = bitcast i32 0 to i32 diff --git a/test/MC/ARM/neon-vld-encoding.s b/test/MC/ARM/neon-vld-encoding.s index 6e55c648ce..648e917057 100644 --- a/test/MC/ARM/neon-vld-encoding.s +++ b/test/MC/ARM/neon-vld-encoding.s @@ -55,60 +55,60 @@ vld1.32 {d5, d6, d7, d8}, [r3], r8 vld1.64 {d6, d7, d8, d9}, [r3:64], r8 -@ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf4] +@ CHECK: vld1.8 {d16}, [r0:64] @ encoding: [0x1f,0x07,0x60,0xf4] @ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf4] @ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x60,0xf4] @ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf4] -@ CHECK: vld1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x60,0xf4] -@ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf4] +@ CHECK: vld1.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x0a,0x60,0xf4] +@ CHECK: vld1.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x0a,0x60,0xf4] @ CHECK: vld1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x60,0xf4] @ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf4] @ CHECK: vld1.8 {d1, d2, d3}, [r3] @ encoding: [0x0f,0x16,0x23,0xf4] -@ CHECK: vld1.16 {d4, d5, d6}, [r3, :64] @ encoding: [0x5f,0x46,0x23,0xf4] +@ CHECK: vld1.16 {d4, d5, d6}, [r3:64] @ encoding: [0x5f,0x46,0x23,0xf4] @ CHECK: vld1.32 {d5, d6, d7}, [r3] @ encoding: [0x8f,0x56,0x23,0xf4] -@ CHECK: vld1.64 {d6, d7, d8}, [r3, :64] @ encoding: [0xdf,0x66,0x23,0xf4] +@ CHECK: vld1.64 {d6, d7, d8}, [r3:64] @ encoding: [0xdf,0x66,0x23,0xf4] @ CHECK: vld1.8 {d1, d2, d3, d4}, [r3] @ encoding: [0x0f,0x12,0x23,0xf4] -@ CHECK: vld1.16 {d4, d5, d6, d7}, [r3, :64] @ encoding: [0x5f,0x42,0x23,0xf4] +@ CHECK: vld1.16 {d4, d5, d6, d7}, [r3:64] @ encoding: [0x5f,0x42,0x23,0xf4] @ CHECK: vld1.32 {d5, d6, d7, d8}, [r3] @ encoding: [0x8f,0x52,0x23,0xf4] -@ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64] @ encoding: [0xdf,0x62,0x23,0xf4] -@ CHECK: vld1.8 {d16}, [r0, :64]! @ encoding: [0x1d,0x07,0x60,0xf4] +@ CHECK: vld1.64 {d6, d7, d8, d9}, [r3:64] @ encoding: [0xdf,0x62,0x23,0xf4] +@ CHECK: vld1.8 {d16}, [r0:64]! @ encoding: [0x1d,0x07,0x60,0xf4] @ CHECK: vld1.16 {d16}, [r0]! @ encoding: [0x4d,0x07,0x60,0xf4] @ CHECK: vld1.32 {d16}, [r0]! @ encoding: [0x8d,0x07,0x60,0xf4] @ CHECK: vld1.64 {d16}, [r0]! @ encoding: [0xcd,0x07,0x60,0xf4] -@ CHECK: vld1.8 {d16, d17}, [r0, :64]! @ encoding: [0x1d,0x0a,0x60,0xf4] -@ CHECK: vld1.16 {d16, d17}, [r0, :128]! @ encoding: [0x6d,0x0a,0x60,0xf4] +@ CHECK: vld1.8 {d16, d17}, [r0:64]! @ encoding: [0x1d,0x0a,0x60,0xf4] +@ CHECK: vld1.16 {d16, d17}, [r0:128]! @ encoding: [0x6d,0x0a,0x60,0xf4] @ CHECK: vld1.32 {d16, d17}, [r0]! @ encoding: [0x8d,0x0a,0x60,0xf4] @ CHECK: vld1.64 {d16, d17}, [r0]! @ encoding: [0xcd,0x0a,0x60,0xf4] -@ CHECK: vld1.8 {d16}, [r0, :64], r5 @ encoding: [0x15,0x07,0x60,0xf4] +@ CHECK: vld1.8 {d16}, [r0:64], r5 @ encoding: [0x15,0x07,0x60,0xf4] @ CHECK: vld1.16 {d16}, [r0], r5 @ encoding: [0x45,0x07,0x60,0xf4] @ CHECK: vld1.32 {d16}, [r0], r5 @ encoding: [0x85,0x07,0x60,0xf4] @ CHECK: vld1.64 {d16}, [r0], r5 @ encoding: [0xc5,0x07,0x60,0xf4] -@ CHECK: vld1.8 {d16, d17}, [r0, :64], r5 @ encoding: [0x15,0x0a,0x60,0xf4] -@ CHECK: vld1.16 {d16, d17}, [r0, :128], r5 @ encoding: [0x65,0x0a,0x60,0xf4] +@ CHECK: vld1.8 {d16, d17}, [r0:64], r5 @ encoding: [0x15,0x0a,0x60,0xf4] +@ CHECK: vld1.16 {d16, d17}, [r0:128], r5 @ encoding: [0x65,0x0a,0x60,0xf4] @ CHECK: vld1.32 {d16, d17}, [r0], r5 @ encoding: [0x85,0x0a,0x60,0xf4] @ CHECK: vld1.64 {d16, d17}, [r0], r5 @ encoding: [0xc5,0x0a,0x60,0xf4] @ CHECK: vld1.8 {d1, d2, d3}, [r3]! @ encoding: [0x0d,0x16,0x23,0xf4] -@ CHECK: vld1.16 {d4, d5, d6}, [r3, :64]! @ encoding: [0x5d,0x46,0x23,0xf4] +@ CHECK: vld1.16 {d4, d5, d6}, [r3:64]! @ encoding: [0x5d,0x46,0x23,0xf4] @ CHECK: vld1.32 {d5, d6, d7}, [r3]! @ encoding: [0x8d,0x56,0x23,0xf4] -@ CHECK: vld1.64 {d6, d7, d8}, [r3, :64]! @ encoding: [0xdd,0x66,0x23,0xf4] +@ CHECK: vld1.64 {d6, d7, d8}, [r3:64]! @ encoding: [0xdd,0x66,0x23,0xf4] @ CHECK: vld1.8 {d1, d2, d3}, [r3], r6 @ encoding: [0x06,0x16,0x23,0xf4] -@ CHECK: vld1.16 {d4, d5, d6}, [r3, :64], r6 @ encoding: [0x56,0x46,0x23,0xf4] +@ CHECK: vld1.16 {d4, d5, d6}, [r3:64], r6 @ encoding: [0x56,0x46,0x23,0xf4] @ CHECK: vld1.32 {d5, d6, d7}, [r3], r6 @ encoding: [0x86,0x56,0x23,0xf4] -@ CHECK: vld1.64 {d6, d7, d8}, [r3, :64], r6 @ encoding: [0xd6,0x66,0x23,0xf4] +@ CHECK: vld1.64 {d6, d7, d8}, [r3:64], r6 @ encoding: [0xd6,0x66,0x23,0xf4] @ CHECK: vld1.8 {d1, d2, d3, d4}, [r3]! @ encoding: [0x0d,0x12,0x23,0xf4] -@ CHECK: vld1.16 {d4, d5, d6, d7}, [r3, :64]! @ encoding: [0x5d,0x42,0x23,0xf4] +@ CHECK: vld1.16 {d4, d5, d6, d7}, [r3:64]! @ encoding: [0x5d,0x42,0x23,0xf4] @ CHECK: vld1.32 {d5, d6, d7, d8}, [r3]! @ encoding: [0x8d,0x52,0x23,0xf4] -@ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64]! @ encoding: [0xdd,0x62,0x23,0xf4] +@ CHECK: vld1.64 {d6, d7, d8, d9}, [r3:64]! @ encoding: [0xdd,0x62,0x23,0xf4] @ CHECK: vld1.8 {d1, d2, d3, d4}, [r3], r8 @ encoding: [0x08,0x12,0x23,0xf4] -@ CHECK: vld1.16 {d4, d5, d6, d7}, [r3, :64], r8 @ encoding: [0x58,0x42,0x23,0xf4] +@ CHECK: vld1.16 {d4, d5, d6, d7}, [r3:64], r8 @ encoding: [0x58,0x42,0x23,0xf4] @ CHECK: vld1.32 {d5, d6, d7, d8}, [r3], r8 @ encoding: [0x88,0x52,0x23,0xf4] -@ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64], r8 @ encoding: [0xd8,0x62,0x23,0xf4] +@ CHECK: vld1.64 {d6, d7, d8, d9}, [r3:64], r8 @ encoding: [0xd8,0x62,0x23,0xf4] vld2.8 {d16, d17}, [r0:64] @@ -132,26 +132,26 @@ vld2.16 {d1, d2, d3, d4}, [r0:128], r6 vld2.32 {q7, q8}, [r0:256], r6 -@ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4] -@ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4] +@ CHECK: vld2.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x08,0x60,0xf4] +@ CHECK: vld2.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x08,0x60,0xf4] @ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf4] -@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf4] -@ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf4] -@ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf4] +@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x1f,0x03,0x60,0xf4] +@ CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128] @ encoding: [0x6f,0x03,0x60,0xf4] +@ CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256] @ encoding: [0xbf,0x03,0x60,0xf4] -@ CHECK: vld2.8 {d19, d20}, [r0, :64]! @ encoding: [0x1d,0x38,0x60,0xf4] -@ CHECK: vld2.16 {d16, d17}, [r0, :128]! @ encoding: [0x6d,0x08,0x60,0xf4] +@ CHECK: vld2.8 {d19, d20}, [r0:64]! @ encoding: [0x1d,0x38,0x60,0xf4] +@ CHECK: vld2.16 {d16, d17}, [r0:128]! @ encoding: [0x6d,0x08,0x60,0xf4] @ CHECK: vld2.32 {d20, d21}, [r0]! @ encoding: [0x8d,0x48,0x60,0xf4] -@ CHECK: vld2.8 {d4, d5, d6, d7}, [r0, :64]! @ encoding: [0x1d,0x43,0x20,0xf4] -@ CHECK: vld2.16 {d1, d2, d3, d4}, [r0, :128]! @ encoding: [0x6d,0x13,0x20,0xf4] -@ CHECK: vld2.32 {d14, d15, d16, d17}, [r0, :256]! @ encoding: [0xbd,0xe3,0x20,0xf4] +@ CHECK: vld2.8 {d4, d5, d6, d7}, [r0:64]! @ encoding: [0x1d,0x43,0x20,0xf4] +@ CHECK: vld2.16 {d1, d2, d3, d4}, [r0:128]! @ encoding: [0x6d,0x13,0x20,0xf4] +@ CHECK: vld2.32 {d14, d15, d16, d17}, [r0:256]! @ encoding: [0xbd,0xe3,0x20,0xf4] -@ CHECK: vld2.8 {d19, d20}, [r0, :64], r6 @ encoding: [0x16,0x38,0x60,0xf4] -@ CHECK: vld2.16 {d16, d17}, [r0, :128], r6 @ encoding: [0x66,0x08,0x60,0xf4] +@ CHECK: vld2.8 {d19, d20}, [r0:64], r6 @ encoding: [0x16,0x38,0x60,0xf4] +@ CHECK: vld2.16 {d16, d17}, [r0:128], r6 @ encoding: [0x66,0x08,0x60,0xf4] @ CHECK: vld2.32 {d20, d21}, [r0], r6 @ encoding: [0x86,0x48,0x60,0xf4] -@ CHECK: vld2.8 {d4, d5, d6, d7}, [r0, :64], r6 @ encoding: [0x16,0x43,0x20,0xf4] -@ CHECK: vld2.16 {d1, d2, d3, d4}, [r0, :128], r6 @ encoding: [0x66,0x13,0x20,0xf4] -@ CHECK: vld2.32 {d14, d15, d16, d17}, [r0, :256], r6 @ encoding: [0xb6,0xe3,0x20,0xf4] +@ CHECK: vld2.8 {d4, d5, d6, d7}, [r0:64], r6 @ encoding: [0x16,0x43,0x20,0xf4] +@ CHECK: vld2.16 {d1, d2, d3, d4}, [r0:128], r6 @ encoding: [0x66,0x13,0x20,0xf4] +@ CHECK: vld2.32 {d14, d15, d16, d17}, [r0:256], r6 @ encoding: [0xb6,0xe3,0x20,0xf4] vld3.8 {d16, d17, d18}, [r1] @@ -179,7 +179,7 @@ @ CHECK: vld3.8 {d16, d17, d18}, [r1] @ encoding: [0x0f,0x04,0x61,0xf4] @ CHECK: vld3.16 {d6, d7, d8}, [r2] @ encoding: [0x4f,0x64,0x22,0xf4] @ CHECK: vld3.32 {d1, d2, d3}, [r3] @ encoding: [0x8f,0x14,0x23,0xf4] -@ CHECK: vld3.8 {d16, d18, d20}, [r0, :64] @ encoding: [0x1f,0x05,0x60,0xf4] +@ CHECK: vld3.8 {d16, d18, d20}, [r0:64] @ encoding: [0x1f,0x05,0x60,0xf4] @ CHECK: vld3.16 {d27, d29, d31}, [r4] @ encoding: [0x4f,0xb5,0x64,0xf4] @ CHECK: vld3.32 {d6, d8, d10}, [r5] @ encoding: [0x8f,0x65,0x25,0xf4] @ CHECK: vld3.8 {d12, d13, d14}, [r6], r1 @ encoding: [0x01,0xc4,0x26,0xf4] @@ -191,7 +191,7 @@ @ CHECK: vld3.8 {d6, d7, d8}, [r8]! @ encoding: [0x0d,0x64,0x28,0xf4] @ CHECK: vld3.16 {d9, d10, d11}, [r7]! @ encoding: [0x4d,0x94,0x27,0xf4] @ CHECK: vld3.32 {d1, d2, d3}, [r6]! @ encoding: [0x8d,0x14,0x26,0xf4] -@ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf4] +@ CHECK: vld3.8 {d16, d18, d20}, [r0:64]! @ encoding: [0x1d,0x05,0x60,0xf4] @ CHECK: vld3.16 {d20, d22, d24}, [r5]! @ encoding: [0x4d,0x45,0x65,0xf4] @ CHECK: vld3.32 {d5, d7, d9}, [r4]! @ encoding: [0x8d,0x55,0x24,0xf4] @@ -217,22 +217,22 @@ vld4.i16 {d16, d18, d20, d22}, [r6], r3 vld4.i32 {d17, d19, d21, d23}, [r9], r4 -@ CHECK: vld4.8 {d16, d17, d18, d19}, [r1, :64] @ encoding: [0x1f,0x00,0x61,0xf4] -@ CHECK: vld4.16 {d16, d17, d18, d19}, [r2, :128] @ encoding: [0x6f,0x00,0x62,0xf4] -@ CHECK: vld4.32 {d16, d17, d18, d19}, [r3, :256] @ encoding: [0xbf,0x00,0x63,0xf4] -@ CHECK: vld4.8 {d17, d19, d21, d23}, [r5, :256] @ encoding: [0x3f,0x11,0x65,0xf4] +@ CHECK: vld4.8 {d16, d17, d18, d19}, [r1:64] @ encoding: [0x1f,0x00,0x61,0xf4] +@ CHECK: vld4.16 {d16, d17, d18, d19}, [r2:128] @ encoding: [0x6f,0x00,0x62,0xf4] +@ CHECK: vld4.32 {d16, d17, d18, d19}, [r3:256] @ encoding: [0xbf,0x00,0x63,0xf4] +@ CHECK: vld4.8 {d17, d19, d21, d23}, [r5:256] @ encoding: [0x3f,0x11,0x65,0xf4] @ CHECK: vld4.16 {d17, d19, d21, d23}, [r7] @ encoding: [0x4f,0x11,0x67,0xf4] @ CHECK: vld4.32 {d16, d18, d20, d22}, [r8] @ encoding: [0x8f,0x01,0x68,0xf4] -@ CHECK: vld4.8 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x1d,0x00,0x61,0xf4] -@ CHECK: vld4.16 {d16, d17, d18, d19}, [r2, :128]! @ encoding: [0x6d,0x00,0x62,0xf4] -@ CHECK: vld4.32 {d16, d17, d18, d19}, [r3, :256]! @ encoding: [0xbd,0x00,0x63,0xf4] -@ CHECK: vld4.8 {d17, d19, d21, d23}, [r5, :256]! @ encoding: [0x3d,0x11,0x65,0xf4] +@ CHECK: vld4.8 {d16, d17, d18, d19}, [r1:64]! @ encoding: [0x1d,0x00,0x61,0xf4] +@ CHECK: vld4.16 {d16, d17, d18, d19}, [r2:128]! @ encoding: [0x6d,0x00,0x62,0xf4] +@ CHECK: vld4.32 {d16, d17, d18, d19}, [r3:256]! @ encoding: [0xbd,0x00,0x63,0xf4] +@ CHECK: vld4.8 {d17, d19, d21, d23}, [r5:256]! @ encoding: [0x3d,0x11,0x65,0xf4] @ CHECK: vld4.16 {d17, d19, d21, d23}, [r7]! @ encoding: [0x4d,0x11,0x67,0xf4] @ CHECK: vld4.32 {d16, d18, d20, d22}, [r8]! @ encoding: [0x8d,0x01,0x68,0xf4] -@ CHECK: vld4.8 {d16, d17, d18, d19}, [r1, :64], r8 @ encoding: [0x18,0x00,0x61,0xf4] +@ CHECK: vld4.8 {d16, d17, d18, d19}, [r1:64], r8 @ encoding: [0x18,0x00,0x61,0xf4] @ CHECK: vld4.16 {d16, d17, d18, d19}, [r2], r7 @ encoding: [0x47,0x00,0x62,0xf4] -@ CHECK: vld4.32 {d16, d17, d18, d19}, [r3, :64], r5 @ encoding: [0x95,0x00,0x63,0xf4] -@ CHECK: vld4.8 {d16, d18, d20, d22}, [r4, :256], r2 @ encoding: [0x32,0x01,0x64,0xf4] +@ CHECK: vld4.32 {d16, d17, d18, d19}, [r3:64], r5 @ encoding: [0x95,0x00,0x63,0xf4] +@ CHECK: vld4.8 {d16, d18, d20, d22}, [r4:256], r2 @ encoding: [0x32,0x01,0x64,0xf4] @ CHECK: vld4.16 {d16, d18, d20, d22}, [r6], r3 @ encoding: [0x43,0x01,0x66,0xf4] @ CHECK: vld4.32 {d17, d19, d21, d23}, [r9], r4 @ encoding: [0x84,0x11,0x69,0xf4] @@ -260,8 +260,8 @@ vld1.16 d12[2], [r2], r2 @ CHECK: vld1.8 {d16[3]}, [r0] @ encoding: [0x6f,0x00,0xe0,0xf4] -@ CHECK: vld1.16 {d16[2]}, [r0, :16] @ encoding: [0x9f,0x04,0xe0,0xf4] -@ CHECK: vld1.32 {d16[1]}, [r0, :32] @ encoding: [0xbf,0x08,0xe0,0xf4] +@ CHECK: vld1.16 {d16[2]}, [r0:16] @ encoding: [0x9f,0x04,0xe0,0xf4] +@ CHECK: vld1.32 {d16[1]}, [r0:32] @ encoding: [0xbf,0x08,0xe0,0xf4] @ CHECK: vld1.8 {d12[6]}, [r2]! @ encoding: [0xcd,0xc0,0xa2,0xf4] @ CHECK: vld1.8 {d12[6]}, [r2], r2 @ encoding: [0xc2,0xc0,0xa2,0xf4] @ CHECK: vld1.16 {d12[3]}, [r2]! @ encoding: [0xcd,0xc4,0xa2,0xf4] @@ -284,12 +284,12 @@ vld2.32 {d22[ ],d23[ ]}, [r5], r4 vld2.32 {d22[ ],d24[ ]}, [r6], r4 -@ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4] -@ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4] +@ CHECK: vld2.8 {d16[1], d17[1]}, [r0:16] @ encoding: [0x3f,0x01,0xe0,0xf4] +@ CHECK: vld2.16 {d16[1], d17[1]}, [r0:32] @ encoding: [0x5f,0x05,0xe0,0xf4] @ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf4] @ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4] -@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4] -@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64]! @ encoding: [0x5d,0x19,0xe0,0xf4] +@ CHECK: vld2.32 {d17[0], d19[0]}, [r0:64] @ encoding: [0x5f,0x19,0xe0,0xf4] +@ CHECK: vld2.32 {d17[0], d19[0]}, [r0:64]! @ encoding: [0x5d,0x19,0xe0,0xf4] @ CHECK: vld2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0xa2,0xf4] @ CHECK: vld2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0xa2,0xf4] @ CHECK: vld2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0xa2,0xf4] @@ -400,14 +400,14 @@ @ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3] @ encoding: [0x8f,0x0b,0xe3,0xf4] @ CHECK: vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7] @ encoding: [0x6f,0x17,0xe7,0xf4] @ CHECK: vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8] @ encoding: [0xcf,0x0b,0xe8,0xf4] -@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]! @ encoding: [0x3d,0x03,0xe1,0xf4] -@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2, :64]! @ encoding: [0x5d,0x07,0xe2,0xf4] -@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :128]! @ encoding: [0xad,0x0b,0xe3,0xf4] +@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]! @ encoding: [0x3d,0x03,0xe1,0xf4] +@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]! @ encoding: [0x5d,0x07,0xe2,0xf4] +@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]! @ encoding: [0xad,0x0b,0xe3,0xf4] @ CHECK: vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]! @ encoding: [0x6d,0x17,0xe7,0xf4] @ CHECK: vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]! @ encoding: [0xcd,0x0b,0xe8,0xf4] -@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32], r8 @ encoding: [0x38,0x03,0xe1,0xf4] +@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8 @ encoding: [0x38,0x03,0xe1,0xf4] @ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7 @ encoding: [0x47,0x07,0xe2,0xf4] -@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :64], r5 @ encoding: [0x95,0x0b,0xe3,0xf4] +@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5 @ encoding: [0x95,0x0b,0xe3,0xf4] @ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3 @ encoding: [0x63,0x07,0xe6,0xf4] @ CHECK: vld4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4 @ encoding: [0xc4,0x1b,0xe9,0xf4] @@ -493,8 +493,8 @@ vld1.f64 {d2-d5}, [r2:128]! vld1.f64 {d2,d3,d4,d5}, [r2:128]! -@ CHECK: vld1.64 {d2, d3, d4, d5}, [r2, :128]! @ encoding: [0xed,0x22,0x22,0xf4] -@ CHECK: vld1.64 {d2, d3, d4, d5}, [r2, :128]! @ encoding: [0xed,0x22,0x22,0xf4] +@ CHECK: vld1.64 {d2, d3, d4, d5}, [r2:128]! @ encoding: [0xed,0x22,0x22,0xf4] +@ CHECK: vld1.64 {d2, d3, d4, d5}, [r2:128]! @ encoding: [0xed,0x22,0x22,0xf4] @ verify that the old incorrect alignment specifier syntax (", :") @@ -502,5 +502,5 @@ vld2.8 {d16, d17}, [r0, :64] vld2.16 {d16, d17}, [r0, :128] -@ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4] -@ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4] +@ CHECK: vld2.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x08,0x60,0xf4] +@ CHECK: vld2.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x08,0x60,0xf4] diff --git a/test/MC/ARM/neon-vst-encoding.s b/test/MC/ARM/neon-vst-encoding.s index 4629721380..ef9f037c53 100644 --- a/test/MC/ARM/neon-vst-encoding.s +++ b/test/MC/ARM/neon-vst-encoding.s @@ -15,19 +15,19 @@ vst1.16 {d16, d17, d18, d19}, [r1:64]! vst1.64 {d16, d17, d18, d19}, [r3], r2 -@ CHECK: vst1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x40,0xf4] +@ CHECK: vst1.8 {d16}, [r0:64] @ encoding: [0x1f,0x07,0x40,0xf4] @ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf4] @ CHECK: vst1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x40,0xf4] @ CHECK: vst1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x40,0xf4] -@ CHECK: vst1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x40,0xf4] -@ CHECK: vst1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x40,0xf4] +@ CHECK: vst1.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x0a,0x40,0xf4] +@ CHECK: vst1.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x0a,0x40,0xf4] @ CHECK: vst1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x40,0xf4] @ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf4] -@ CHECK: vst1.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x06,0x40,0xf4] -@ CHECK: vst1.8 {d16, d17, d18}, [r0, :64]! @ encoding: [0x1d,0x06,0x40,0xf4] +@ CHECK: vst1.8 {d16, d17, d18}, [r0:64] @ encoding: [0x1f,0x06,0x40,0xf4] +@ CHECK: vst1.8 {d16, d17, d18}, [r0:64]! @ encoding: [0x1d,0x06,0x40,0xf4] @ CHECK: vst1.8 {d16, d17, d18}, [r0], r3 @ encoding: [0x03,0x06,0x40,0xf4] -@ CHECK: vst1.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x02,0x40,0xf4] -@ CHECK: vst1.16 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x5d,0x02,0x41,0xf4] +@ CHECK: vst1.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x1f,0x02,0x40,0xf4] +@ CHECK: vst1.16 {d16, d17, d18, d19}, [r1:64]! @ encoding: [0x5d,0x02,0x41,0xf4] @ CHECK: vst1.64 {d16, d17, d18, d19}, [r3], r2 @ encoding: [0xc2,0x02,0x43,0xf4] @@ -44,18 +44,18 @@ vst2.16 {d18-d21}, [r0:128]! vst2.32 {q4, q5}, [r0:256]! -@ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf4] -@ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf4] +@ CHECK: vst2.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x08,0x40,0xf4] +@ CHECK: vst2.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x08,0x40,0xf4] @ CHECK: vst2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x40,0xf4] -@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x40,0xf4] -@ CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x40,0xf4] -@ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf4] -@ CHECK: vst2.8 {d16, d17}, [r0, :64]! @ encoding: [0x1d,0x08,0x40,0xf4] -@ CHECK: vst2.16 {d30, d31}, [r0, :128]! @ encoding: [0x6d,0xe8,0x40,0xf4] +@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x1f,0x03,0x40,0xf4] +@ CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128] @ encoding: [0x6f,0x03,0x40,0xf4] +@ CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256] @ encoding: [0xbf,0x03,0x40,0xf4] +@ CHECK: vst2.8 {d16, d17}, [r0:64]! @ encoding: [0x1d,0x08,0x40,0xf4] +@ CHECK: vst2.16 {d30, d31}, [r0:128]! @ encoding: [0x6d,0xe8,0x40,0xf4] @ CHECK: vst2.32 {d14, d15}, [r0]! @ encoding: [0x8d,0xe8,0x00,0xf4] -@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64]! @ encoding: [0x1d,0x03,0x40,0xf4] -@ CHECK: vst2.16 {d18, d19, d20, d21}, [r0, :128]! @ encoding: [0x6d,0x23,0x40,0xf4] -@ CHECK: vst2.32 {d8, d9, d10, d11}, [r0, :256]! @ encoding: [0xbd,0x83,0x00,0xf4] +@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64]! @ encoding: [0x1d,0x03,0x40,0xf4] +@ CHECK: vst2.16 {d18, d19, d20, d21}, [r0:128]! @ encoding: [0x6d,0x23,0x40,0xf4] +@ CHECK: vst2.32 {d8, d9, d10, d11}, [r0:256]! @ encoding: [0xbd,0x83,0x00,0xf4] vst3.8 {d16, d17, d18}, [r1] @@ -82,7 +82,7 @@ @ CHECK: vst3.8 {d16, d17, d18}, [r1] @ encoding: [0x0f,0x04,0x41,0xf4] @ CHECK: vst3.16 {d6, d7, d8}, [r2] @ encoding: [0x4f,0x64,0x02,0xf4] @ CHECK: vst3.32 {d1, d2, d3}, [r3] @ encoding: [0x8f,0x14,0x03,0xf4] -@ CHECK: vst3.8 {d16, d18, d20}, [r0, :64] @ encoding: [0x1f,0x05,0x40,0xf4] +@ CHECK: vst3.8 {d16, d18, d20}, [r0:64] @ encoding: [0x1f,0x05,0x40,0xf4] @ CHECK: vst3.16 {d27, d29, d31}, [r4] @ encoding: [0x4f,0xb5,0x44,0xf4] @ CHECK: vst3.32 {d6, d8, d10}, [r5] @ encoding: [0x8f,0x65,0x05,0xf4] @ CHECK: vst3.8 {d12, d13, d14}, [r6], r1 @ encoding: [0x01,0xc4,0x06,0xf4] @@ -94,7 +94,7 @@ @ CHECK: vst3.8 {d6, d7, d8}, [r8]! @ encoding: [0x0d,0x64,0x08,0xf4] @ CHECK: vst3.16 {d9, d10, d11}, [r7]! @ encoding: [0x4d,0x94,0x07,0xf4] @ CHECK: vst3.32 {d1, d2, d3}, [r6]! @ encoding: [0x8d,0x14,0x06,0xf4] -@ CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x40,0xf4] +@ CHECK: vst3.8 {d16, d18, d20}, [r0:64]! @ encoding: [0x1d,0x05,0x40,0xf4] @ CHECK: vst3.16 {d20, d22, d24}, [r5]! @ encoding: [0x4d,0x45,0x45,0xf4] @ CHECK: vst3.32 {d5, d7, d9}, [r4]! @ encoding: [0x8d,0x55,0x04,0xf4] @@ -120,22 +120,22 @@ vst4.i16 {d16, d18, d20, d22}, [r6], r3 vst4.i32 {d17, d19, d21, d23}, [r9], r4 -@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64] @ encoding: [0x1f,0x00,0x41,0xf4] -@ CHECK: vst4.16 {d16, d17, d18, d19}, [r2, :128] @ encoding: [0x6f,0x00,0x42,0xf4] -@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :256] @ encoding: [0xbf,0x00,0x43,0xf4] -@ CHECK: vst4.8 {d17, d19, d21, d23}, [r5, :256] @ encoding: [0x3f,0x11,0x45,0xf4] +@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1:64] @ encoding: [0x1f,0x00,0x41,0xf4] +@ CHECK: vst4.16 {d16, d17, d18, d19}, [r2:128] @ encoding: [0x6f,0x00,0x42,0xf4] +@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3:256] @ encoding: [0xbf,0x00,0x43,0xf4] +@ CHECK: vst4.8 {d17, d19, d21, d23}, [r5:256] @ encoding: [0x3f,0x11,0x45,0xf4] @ CHECK: vst4.16 {d17, d19, d21, d23}, [r7] @ encoding: [0x4f,0x11,0x47,0xf4] @ CHECK: vst4.32 {d16, d18, d20, d22}, [r8] @ encoding: [0x8f,0x01,0x48,0xf4] -@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x1d,0x00,0x41,0xf4] -@ CHECK: vst4.16 {d16, d17, d18, d19}, [r2, :128]! @ encoding: [0x6d,0x00,0x42,0xf4] -@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :256]! @ encoding: [0xbd,0x00,0x43,0xf4] -@ CHECK: vst4.8 {d17, d19, d21, d23}, [r5, :256]! @ encoding: [0x3d,0x11,0x45,0xf4] +@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1:64]! @ encoding: [0x1d,0x00,0x41,0xf4] +@ CHECK: vst4.16 {d16, d17, d18, d19}, [r2:128]! @ encoding: [0x6d,0x00,0x42,0xf4] +@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3:256]! @ encoding: [0xbd,0x00,0x43,0xf4] +@ CHECK: vst4.8 {d17, d19, d21, d23}, [r5:256]! @ encoding: [0x3d,0x11,0x45,0xf4] @ CHECK: vst4.16 {d17, d19, d21, d23}, [r7]! @ encoding: [0x4d,0x11,0x47,0xf4] @ CHECK: vst4.32 {d16, d18, d20, d22}, [r8]! @ encoding: [0x8d,0x01,0x48,0xf4] -@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64], r8 @ encoding: [0x18,0x00,0x41,0xf4] +@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1:64], r8 @ encoding: [0x18,0x00,0x41,0xf4] @ CHECK: vst4.16 {d16, d17, d18, d19}, [r2], r7 @ encoding: [0x47,0x00,0x42,0xf4] -@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :64], r5 @ encoding: [0x95,0x00,0x43,0xf4] -@ CHECK: vst4.8 {d16, d18, d20, d22}, [r4, :256], r2 @ encoding: [0x32,0x01,0x44,0xf4] +@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3:64], r5 @ encoding: [0x95,0x00,0x43,0xf4] +@ CHECK: vst4.8 {d16, d18, d20, d22}, [r4:256], r2 @ encoding: [0x32,0x01,0x44,0xf4] @ CHECK: vst4.16 {d16, d18, d20, d22}, [r6], r3 @ encoding: [0x43,0x01,0x46,0xf4] @ CHECK: vst4.32 {d17, d19, d21, d23}, [r9], r4 @ encoding: [0x84,0x11,0x49,0xf4] @@ -157,22 +157,22 @@ vst2.16 {d2[1], d4[1]}, [r3], r5 vst2.u32 {d5[0], d7[0]}, [r4:64], r7 -@ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4] -@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4] +@ CHECK: vst2.8 {d16[1], d17[1]}, [r0:16] @ encoding: [0x3f,0x01,0xc0,0xf4] +@ CHECK: vst2.16 {d16[1], d17[1]}, [r0:32] @ encoding: [0x5f,0x05,0xc0,0xf4] @ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4] @ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] -@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] +@ CHECK: vst2.32 {d17[0], d19[0]}, [r0:64] @ encoding: [0x5f,0x19,0xc0,0xf4] @ CHECK: vst2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0x82,0xf4] @ CHECK: vst2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0x82,0xf4] @ CHECK: vst2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0x82,0xf4] @ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] -@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] +@ CHECK: vst2.32 {d17[0], d19[0]}, [r0:64] @ encoding: [0x5f,0x19,0xc0,0xf4] @ CHECK: vst2.16 {d7[1], d9[1]}, [r1]! @ encoding: [0x6d,0x75,0x81,0xf4] -@ CHECK: vst2.32 {d6[0], d8[0]}, [r2, :64]! @ encoding: [0x5d,0x69,0x82,0xf4] +@ CHECK: vst2.32 {d6[0], d8[0]}, [r2:64]! @ encoding: [0x5d,0x69,0x82,0xf4] @ CHECK: vst2.16 {d2[1], d4[1]}, [r3], r5 @ encoding: [0x65,0x25,0x83,0xf4] -@ CHECK: vst2.32 {d5[0], d7[0]}, [r4, :64], r7 @ encoding: [0x57,0x59,0x84,0xf4] +@ CHECK: vst2.32 {d5[0], d7[0]}, [r4:64], r7 @ encoding: [0x57,0x59,0x84,0xf4] vst3.8 {d16[1], d17[1], d18[1]}, [r1] @@ -233,14 +233,14 @@ @ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3] @ encoding: [0x8f,0x0b,0xc3,0xf4] @ CHECK: vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7] @ encoding: [0x6f,0x17,0xc7,0xf4] @ CHECK: vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8] @ encoding: [0xcf,0x0b,0xc8,0xf4] -@ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]! @ encoding: [0x3d,0x03,0xc1,0xf4] -@ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2, :64]! @ encoding: [0x5d,0x07,0xc2,0xf4] -@ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :128]! @ encoding: [0xad,0x0b,0xc3,0xf4] +@ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]! @ encoding: [0x3d,0x03,0xc1,0xf4] +@ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]! @ encoding: [0x5d,0x07,0xc2,0xf4] +@ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]! @ encoding: [0xad,0x0b,0xc3,0xf4] @ CHECK: vst4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]! @ encoding: [0x6d,0x17,0xc7,0xf4] @ CHECK: vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]! @ encoding: [0xcd,0x0b,0xc8,0xf4] -@ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32], r8 @ encoding: [0x38,0x03,0xc1,0xf4] +@ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8 @ encoding: [0x38,0x03,0xc1,0xf4] @ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7 @ encoding: [0x47,0x07,0xc2,0xf4] -@ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :64], r5 @ encoding: [0x95,0x0b,0xc3,0xf4] +@ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5 @ encoding: [0x95,0x0b,0xc3,0xf4] @ CHECK: vst4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3 @ encoding: [0x63,0x07,0xc6,0xf4] @ CHECK: vst4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4 @ encoding: [0xc4,0x1b,0xc9,0xf4] @@ -272,14 +272,14 @@ vst1.32 {d9[1]}, [r3:32] vst1.32 {d27[1]}, [r9:32]! vst1.32 {d27[1]}, [r3:32], r5 -@ CHECK: vst1.32 {d9[1]}, [r3, :32] @ encoding: [0xbf,0x98,0x83,0xf4] -@ CHECK: vst1.32 {d27[1]}, [r9, :32]! @ encoding: [0xbd,0xb8,0xc9,0xf4] -@ CHECK: vst1.32 {d27[1]}, [r3, :32], r5 @ encoding: [0xb5,0xb8,0xc3,0xf4] +@ CHECK: vst1.32 {d9[1]}, [r3:32] @ encoding: [0xbf,0x98,0x83,0xf4] +@ CHECK: vst1.32 {d27[1]}, [r9:32]! @ encoding: [0xbd,0xb8,0xc9,0xf4] +@ CHECK: vst1.32 {d27[1]}, [r3:32], r5 @ encoding: [0xb5,0xb8,0xc3,0xf4] @ verify that the old incorrect alignment specifier syntax (", :") @ still gets accepted. vst2.8 {d16, d17}, [r0, :64] vst2.16 {d16, d17}, [r0, :128] -@ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf4] -@ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf4]
\ No newline at end of file +@ CHECK: vst2.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x08,0x40,0xf4] +@ CHECK: vst2.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x08,0x40,0xf4]
\ No newline at end of file diff --git a/test/MC/ARM/neont2-vld-encoding.s b/test/MC/ARM/neont2-vld-encoding.s index 7f7a099de9..7db8552781 100644 --- a/test/MC/ARM/neont2-vld-encoding.s +++ b/test/MC/ARM/neont2-vld-encoding.s @@ -3,7 +3,7 @@ .code 16 -@ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf9] +@ CHECK: vld1.8 {d16}, [r0:64] @ encoding: [0x1f,0x07,0x60,0xf9] vld1.8 {d16}, [r0:64] @ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf9] vld1.16 {d16}, [r0] @@ -11,37 +11,37 @@ vld1.32 {d16}, [r0] @ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf9] vld1.64 {d16}, [r0] -@ CHECK: vld1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x60,0xf9] +@ CHECK: vld1.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x0a,0x60,0xf9] vld1.8 {d16, d17}, [r0:64] -@ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf9] +@ CHECK: vld1.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x0a,0x60,0xf9] vld1.16 {d16, d17}, [r0:128] @ CHECK: vld1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x60,0xf9] vld1.32 {d16, d17}, [r0] @ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf9] vld1.64 {d16, d17}, [r0] -@ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf9] +@ CHECK: vld2.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x08,0x60,0xf9] vld2.8 {d16, d17}, [r0:64] -@ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf9] +@ CHECK: vld2.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x08,0x60,0xf9] vld2.16 {d16, d17}, [r0:128] @ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf9] vld2.32 {d16, d17}, [r0] -@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf9] +@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x1f,0x03,0x60,0xf9] vld2.8 {d16, d17, d18, d19}, [r0:64] -@ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf9] +@ CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128] @ encoding: [0x6f,0x03,0x60,0xf9] vld2.16 {d16, d17, d18, d19}, [r0:128] -@ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf9] +@ CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256] @ encoding: [0xbf,0x03,0x60,0xf9] vld2.32 {d16, d17, d18, d19}, [r0:256] -@ CHECK: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf9] +@ CHECK: vld3.8 {d16, d17, d18}, [r0:64] @ encoding: [0x1f,0x04,0x60,0xf9] vld3.8 {d16, d17, d18}, [r0:64] @ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x60,0xf9] vld3.16 {d16, d17, d18}, [r0] @ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x60,0xf9] vld3.32 {d16, d17, d18}, [r0] -@ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf9] +@ CHECK: vld3.8 {d16, d18, d20}, [r0:64]! @ encoding: [0x1d,0x05,0x60,0xf9] vld3.8 {d16, d18, d20}, [r0:64]! -@ CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x60,0xf9] +@ CHECK: vld3.8 {d17, d19, d21}, [r0:64]! @ encoding: [0x1d,0x15,0x60,0xf9] vld3.8 {d17, d19, d21}, [r0:64]! @ CHECK: vld3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x60,0xf9] vld3.16 {d16, d18, d20}, [r0]! @@ -52,15 +52,15 @@ @ CHECK: vld3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x60,0xf9] vld3.32 {d17, d19, d21}, [r0]! -@ CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x60,0xf9] +@ CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x1f,0x00,0x60,0xf9] vld4.8 {d16, d17, d18, d19}, [r0:64] -@ CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x60,0xf9] +@ CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128] @ encoding: [0x6f,0x00,0x60,0xf9] vld4.16 {d16, d17, d18, d19}, [r0:128] -@ CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x00,0x60,0xf9] +@ CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256] @ encoding: [0xbf,0x00,0x60,0xf9] vld4.32 {d16, d17, d18, d19}, [r0:256] -@ CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x60,0xf9] +@ CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]! @ encoding: [0x3d,0x01,0x60,0xf9] vld4.8 {d16, d18, d20, d22}, [r0:256]! -@ CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x60,0xf9] +@ CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]! @ encoding: [0x3d,0x11,0x60,0xf9] vld4.8 {d17, d19, d21, d23}, [r0:256]! @ CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x60,0xf9] vld4.16 {d16, d18, d20, d22}, [r0]! @@ -73,20 +73,20 @@ @ CHECK: vld1.8 {d16[3]}, [r0] @ encoding: [0x6f,0x00,0xe0,0xf9] vld1.8 {d16[3]}, [r0] -@ CHECK: vld1.16 {d16[2]}, [r0, :16] @ encoding: [0x9f,0x04,0xe0,0xf9] +@ CHECK: vld1.16 {d16[2]}, [r0:16] @ encoding: [0x9f,0x04,0xe0,0xf9] vld1.16 {d16[2]}, [r0:16] -@ CHECK: vld1.32 {d16[1]}, [r0, :32] @ encoding: [0xbf,0x08,0xe0,0xf9] +@ CHECK: vld1.32 {d16[1]}, [r0:32] @ encoding: [0xbf,0x08,0xe0,0xf9] vld1.32 {d16[1]}, [r0:32] -@ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf9] +@ CHECK: vld2.8 {d16[1], d17[1]}, [r0:16] @ encoding: [0x3f,0x01,0xe0,0xf9] vld2.8 {d16[1], d17[1]}, [r0:16] -@ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf9] +@ CHECK: vld2.16 {d16[1], d17[1]}, [r0:32] @ encoding: [0x5f,0x05,0xe0,0xf9] vld2.16 {d16[1], d17[1]}, [r0:32] @ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf9] vld2.32 {d16[1], d17[1]}, [r0] @ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf9] vld2.16 {d17[1], d19[1]}, [r0] -@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf9] +@ CHECK: vld2.32 {d17[0], d19[0]}, [r0:64] @ encoding: [0x5f,0x19,0xe0,0xf9] vld2.32 {d17[0], d19[0]}, [r0:64] @ CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xe0,0xf9] @@ -100,13 +100,13 @@ @ CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] @ encoding: [0xcf,0x1a,0xe0,0xf9] vld3.32 {d17[1], d19[1], d21[1]}, [r0] -@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xe0,0xf9] +@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] @ encoding: [0x3f,0x03,0xe0,0xf9] vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] @ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xe0,0xf9] vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] -@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xe0,0xf9] +@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] @ encoding: [0xaf,0x0b,0xe0,0xf9] vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] -@ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] @ encoding: [0x7f,0x07,0xe0,0xf9] +@ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64] @ encoding: [0x7f,0x07,0xe0,0xf9] vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64] @ CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xe0,0xf9] vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] diff --git a/test/MC/ARM/neont2-vst-encoding.s b/test/MC/ARM/neont2-vst-encoding.s index fca7d5ed39..9adf7514f4 100644 --- a/test/MC/ARM/neont2-vst-encoding.s +++ b/test/MC/ARM/neont2-vst-encoding.s @@ -3,7 +3,7 @@ .code 16 -@ CHECK: vst1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x40,0xf9] +@ CHECK: vst1.8 {d16}, [r0:64] @ encoding: [0x1f,0x07,0x40,0xf9] vst1.8 {d16}, [r0:64] @ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf9] vst1.16 {d16}, [r0] @@ -11,37 +11,37 @@ vst1.32 {d16}, [r0] @ CHECK: vst1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x40,0xf9] vst1.64 {d16}, [r0] -@ CHECK: vst1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x40,0xf9] +@ CHECK: vst1.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x0a,0x40,0xf9] vst1.8 {d16, d17}, [r0:64] -@ CHECK: vst1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x40,0xf9] +@ CHECK: vst1.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x0a,0x40,0xf9] vst1.16 {d16, d17}, [r0:128] @ CHECK: vst1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x40,0xf9] vst1.32 {d16, d17}, [r0] @ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf9] vst1.64 {d16, d17}, [r0] -@ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf9] +@ CHECK: vst2.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x08,0x40,0xf9] vst2.8 {d16, d17}, [r0:64] -@ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf9] +@ CHECK: vst2.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x08,0x40,0xf9] vst2.16 {d16, d17}, [r0:128] @ CHECK: vst2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x40,0xf9] vst2.32 {d16, d17}, [r0] -@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x40,0xf9] +@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x1f,0x03,0x40,0xf9] vst2.8 {d16, d17, d18, d19}, [r0:64] -@ CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x40,0xf9] +@ CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128] @ encoding: [0x6f,0x03,0x40,0xf9] vst2.16 {d16, d17, d18, d19}, [r0:128] -@ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf9] +@ CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256] @ encoding: [0xbf,0x03,0x40,0xf9] vst2.32 {d16, d17, d18, d19}, [r0:256] -@ CHECK: vst3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x40,0xf9] +@ CHECK: vst3.8 {d16, d17, d18}, [r0:64] @ encoding: [0x1f,0x04,0x40,0xf9] vst3.8 {d16, d17, d18}, [r0:64] @ CHECK: vst3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x40,0xf9] vst3.16 {d16, d17, d18}, [r0] @ CHECK: vst3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x40,0xf9] vst3.32 {d16, d17, d18}, [r0] -@ CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x40,0xf9] +@ CHECK: vst3.8 {d16, d18, d20}, [r0:64]! @ encoding: [0x1d,0x05,0x40,0xf9] vst3.8 {d16, d18, d20}, [r0:64]! -@ CHECK: vst3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x40,0xf9] +@ CHECK: vst3.8 {d17, d19, d21}, [r0:64]! @ encoding: [0x1d,0x15,0x40,0xf9] vst3.8 {d17, d19, d21}, [r0:64]! @ CHECK: vst3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x40,0xf9] vst3.16 {d16, d18, d20}, [r0]! @@ -52,13 +52,13 @@ @ CHECK: vst3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x40,0xf9] vst3.32 {d17, d19, d21}, [r0]! -@ CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x40,0xf9] +@ CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x1f,0x00,0x40,0xf9] vst4.8 {d16, d17, d18, d19}, [r0:64] -@ CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x40,0xf9] +@ CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128] @ encoding: [0x6f,0x00,0x40,0xf9] vst4.16 {d16, d17, d18, d19}, [r0:128] -@ CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x40,0xf9] +@ CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]! @ encoding: [0x3d,0x01,0x40,0xf9] vst4.8 {d16, d18, d20, d22}, [r0:256]! -@ CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x40,0xf9] +@ CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]! @ encoding: [0x3d,0x11,0x40,0xf9] vst4.8 {d17, d19, d21, d23}, [r0:256]! @ CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x40,0xf9] vst4.16 {d16, d18, d20, d22}, [r0]! @@ -69,15 +69,15 @@ @ CHECK: vst4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x40,0xf9] vst4.32 {d17, d19, d21, d23}, [r0]! -@ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf9] +@ CHECK: vst2.8 {d16[1], d17[1]}, [r0:16] @ encoding: [0x3f,0x01,0xc0,0xf9] vst2.8 {d16[1], d17[1]}, [r0:16] -@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf9] +@ CHECK: vst2.16 {d16[1], d17[1]}, [r0:32] @ encoding: [0x5f,0x05,0xc0,0xf9] vst2.16 {d16[1], d17[1]}, [r0:32] @ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf9] vst2.32 {d16[1], d17[1]}, [r0] @ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf9] vst2.16 {d17[1], d19[1]}, [r0] -@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf9] +@ CHECK: vst2.32 {d17[0], d19[0]}, [r0:64] @ encoding: [0x5f,0x19,0xc0,0xf9] vst2.32 {d17[0], d19[0]}, [r0:64] @ CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xc0,0xf9] @@ -91,13 +91,13 @@ @ CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0] @ encoding: [0x4f,0x0a,0xc0,0xf9] vst3.32 {d16[0], d18[0], d20[0]}, [r0] -@ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xc0,0xf9] +@ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] @ encoding: [0x3f,0x03,0xc0,0xf9] vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] @ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xc0,0xf9] vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] -@ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xc0,0xf9] +@ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] @ encoding: [0xaf,0x0b,0xc0,0xf9] vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] -@ CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ encoding: [0xff,0x17,0xc0,0xf9] +@ CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] @ encoding: [0xff,0x17,0xc0,0xf9] vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] @ CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf9] vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] diff --git a/test/MC/Disassembler/ARM/neon-tests.txt b/test/MC/Disassembler/ARM/neon-tests.txt index a7b6b1ccb4..65e9954ac6 100644 --- a/test/MC/Disassembler/ARM/neon-tests.txt +++ b/test/MC/Disassembler/ARM/neon-tests.txt @@ -21,10 +21,10 @@ # CHECK: vld4.8 {d4, d6, d8, d10}, [r2] 0x0f 0x41 0x22 0xf4 -# CHECK: vld1.32 {d3[], d4[]}, [r0, :32]! +# CHECK: vld1.32 {d3[], d4[]}, [r0:32]! 0xbd 0x3c 0xa0 0xf4 -# CHECK: vld4.16 {d3[], d5[], d7[], d9[]}, [r0, :64]! +# CHECK: vld4.16 {d3[], d5[], d7[], d9[]}, [r0:64]! 0x7d 0x3f 0xa0 0xf4 # CHECK: vorr d0, d15, d15 @@ -75,7 +75,7 @@ # CHECK: vbic.i32 q2, #0xa900 0x79 0x43 0x82 0xf3 -# CHECK: vst2.32 {d16, d18}, [r2, :64], r2 +# CHECK: vst2.32 {d16, d18}, [r2:64], r2 0x92 0x9 0x42 0xf4 # CHECK: vmov.s8 r0, d8[1] diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt index 649424af22..cd5f418b56 100644 --- a/test/MC/Disassembler/ARM/neon.txt +++ b/test/MC/Disassembler/ARM/neon.txt @@ -1638,7 +1638,7 @@ 0x1f 0x07 0x60 0xf4 -# CHECK: vld1.8 {d16}, [r0, :64] +# CHECK: vld1.8 {d16}, [r0:64] 0x4f 0x07 0x60 0xf4 # CHECK: vld1.16 {d16}, [r0] 0x8f 0x07 0x60 0xf4 @@ -1646,37 +1646,37 @@ 0xcf 0x07 0x60 0xf4 # CHECK: vld1.64 {d16}, [r0] 0x1f 0x0a 0x60 0xf4 -# CHECK: vld1.8 {d16, d17}, [r0, :64] +# CHECK: vld1.8 {d16, d17}, [r0:64] 0x6f 0x0a 0x60 0xf4 -# CHECK: vld1.16 {d16, d17}, [r0, :128] +# CHECK: vld1.16 {d16, d17}, [r0:128] 0x8f 0x0a 0x60 0xf4 # CHECK: vld1.32 {d16, d17}, [r0] 0xcf 0x0a 0x60 0xf4 # CHECK: vld1.64 {d16, d17}, [r0] 0x1f 0x08 0x60 0xf4 -# CHECK: vld2.8 {d16, d17}, [r0, :64] +# CHECK: vld2.8 {d16, d17}, [r0:64] 0x6f 0x08 0x60 0xf4 -# CHECK: vld2.16 {d16, d17}, [r0, :128] +# CHECK: vld2.16 {d16, d17}, [r0:128] 0x8f 0x08 0x60 0xf4 # CHECK: vld2.32 {d16, d17}, [r0] 0x1f 0x03 0x60 0xf4 -# CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64] 0x6f 0x03 0x60 0xf4 -# CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128] 0xbf 0x03 0x60 0xf4 -# CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] +# CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256] 0x1f 0x04 0x60 0xf4 -# CHECK: vld3.8 {d16, d17, d18}, [r0, :64] +# CHECK: vld3.8 {d16, d17, d18}, [r0:64] 0x4f 0x04 0x60 0xf4 # CHECK: vld3.16 {d16, d17, d18}, [r0] 0x8f 0x04 0x60 0xf4 # CHECK: vld3.32 {d16, d17, d18}, [r0] 0x1d 0x05 0x60 0xf4 -# CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! +# CHECK: vld3.8 {d16, d18, d20}, [r0:64]! 0x1d 0x15 0x60 0xf4 -# CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! +# CHECK: vld3.8 {d17, d19, d21}, [r0:64]! 0x4d 0x05 0x60 0xf4 # CHECK: vld3.16 {d16, d18, d20}, [r0]! 0x4d 0x15 0x60 0xf4 @@ -1687,15 +1687,15 @@ # CHECK: vld3.32 {d17, d19, d21}, [r0]! 0x1f 0x00 0x60 0xf4 -# CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64] 0x6f 0x00 0x60 0xf4 -# CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128] 0xbf 0x00 0x60 0xf4 -# CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] +# CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256] 0x3d 0x01 0x60 0xf4 -# CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! +# CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]! 0x3d 0x11 0x60 0xf4 -# CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! +# CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]! 0x4d 0x01 0x60 0xf4 # CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! 0x4d 0x11 0x60 0xf4 @@ -1708,20 +1708,20 @@ 0x6f 0x00 0xe0 0xf4 # CHECK: vld1.8 {d16[3]}, [r0] 0x9f 0x04 0xe0 0xf4 -# CHECK: vld1.16 {d16[2]}, [r0, :16] +# CHECK: vld1.16 {d16[2]}, [r0:16] 0xbf 0x08 0xe0 0xf4 -# CHECK: vld1.32 {d16[1]}, [r0, :32] +# CHECK: vld1.32 {d16[1]}, [r0:32] 0x3f 0x01 0xe0 0xf4 -# CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] +# CHECK: vld2.8 {d16[1], d17[1]}, [r0:16] 0x5f 0x05 0xe0 0xf4 -# CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] +# CHECK: vld2.16 {d16[1], d17[1]}, [r0:32] 0x8f 0x09 0xe0 0xf4 # CHECK: vld2.32 {d16[1], d17[1]}, [r0] 0x6f 0x15 0xe0 0xf4 # CHECK: vld2.16 {d17[1], d19[1]}, [r0] 0x5f 0x19 0xe0 0xf4 -# CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] +# CHECK: vld2.32 {d17[0], d19[0]}, [r0:64] 0x2f 0x02 0xe0 0xf4 # CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] @@ -1754,44 +1754,44 @@ 0xa5 0x0e 0xa4 0xf4 0x3f 0x03 0xe0 0xf4 -# CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +# CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] 0x4f 0x07 0xe0 0xf4 # CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] 0xaf 0x0b 0xe0 0xf4 -# CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +# CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] 0x7f 0x07 0xe0 0xf4 -# CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] +# CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64] 0x4f 0x1b 0xe0 0xf4 # CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] 0x0f 0x0f 0xa4 0xf4 # CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4] 0x3f 0x0f 0xa4 0xf4 -# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32] +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32] 0x1d 0x0f 0xa4 0xf4 -# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4, :32]! +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! 0x35 0x0f 0xa4 0xf4 -# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32], r5 +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r5 0x4f 0x0f 0xa4 0xf4 # CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4] 0x7f 0x0f 0xa4 0xf4 -# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64] +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64] 0x5d 0x0f 0xa4 0xf4 -# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4, :64]! +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! 0x75 0x0f 0xa4 0xf4 -# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64], r5 +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r5 0x8f 0x0f 0xa4 0xf4 # CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4] 0xbf 0x0f 0xa4 0xf4 -# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :64] +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64] 0xdd 0x0f 0xa4 0xf4 -# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4, :128]! +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]! 0xf5 0x0f 0xa4 0xf4 -# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :128], r5 +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r5 0x1f 0x07 0x40 0xf4 -# CHECK: vst1.8 {d16}, [r0, :64] +# CHECK: vst1.8 {d16}, [r0:64] 0x4f 0x07 0x40 0xf4 # CHECK: vst1.16 {d16}, [r0] 0x8f 0x07 0x40 0xf4 @@ -1799,37 +1799,37 @@ 0xcf 0x07 0x40 0xf4 # CHECK: vst1.64 {d16}, [r0] 0x1f 0x0a 0x40 0xf4 -# CHECK: vst1.8 {d16, d17}, [r0, :64] +# CHECK: vst1.8 {d16, d17}, [r0:64] 0x6f 0x0a 0x40 0xf4 -# CHECK: vst1.16 {d16, d17}, [r0, :128] +# CHECK: vst1.16 {d16, d17}, [r0:128] 0x8f 0x0a 0x40 0xf4 # CHECK: vst1.32 {d16, d17}, [r0] 0xcf 0x0a 0x40 0xf4 # CHECK: vst1.64 {d16, d17}, [r0] 0x1f 0x08 0x40 0xf4 -# CHECK: vst2.8 {d16, d17}, [r0, :64] +# CHECK: vst2.8 {d16, d17}, [r0:64] 0x6f 0x08 0x40 0xf4 -# CHECK: vst2.16 {d16, d17}, [r0, :128] +# CHECK: vst2.16 {d16, d17}, [r0:128] 0x8f 0x08 0x40 0xf4 # CHECK: vst2.32 {d16, d17}, [r0] 0x1f 0x03 0x40 0xf4 -# CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64] 0x6f 0x03 0x40 0xf4 -# CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128] 0xbf 0x03 0x40 0xf4 -# CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] +# CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256] 0x1f 0x04 0x40 0xf4 -# CHECK: vst3.8 {d16, d17, d18}, [r0, :64] +# CHECK: vst3.8 {d16, d17, d18}, [r0:64] 0x4f 0x04 0x40 0xf4 # CHECK: vst3.16 {d16, d17, d18}, [r0] 0x8f 0x04 0x40 0xf4 # CHECK: vst3.32 {d16, d17, d18}, [r0] 0x1d 0x05 0x40 0xf4 -# CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! +# CHECK: vst3.8 {d16, d18, d20}, [r0:64]! 0x1d 0x15 0x40 0xf4 -# CHECK: vst3.8 {d17, d19, d21}, [r0, :64]! +# CHECK: vst3.8 {d17, d19, d21}, [r0:64]! 0x4d 0x05 0x40 0xf4 # CHECK: vst3.16 {d16, d18, d20}, [r0]! 0x4d 0x15 0x40 0xf4 @@ -1840,13 +1840,13 @@ # CHECK: vst3.32 {d17, d19, d21}, [r0]! 0x1f 0x00 0x40 0xf4 -# CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64] 0x6f 0x00 0x40 0xf4 -# CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128] 0x3d 0x01 0x40 0xf4 -# CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! +# CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]! 0x3d 0x11 0x40 0xf4 -# CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]! +# CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]! 0x4d 0x01 0x40 0xf4 # CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! 0x4d 0x11 0x40 0xf4 @@ -1857,15 +1857,15 @@ # CHECK: vst4.32 {d17, d19, d21, d23}, [r0]! 0x3f 0x01 0xc0 0xf4 -# CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] +# CHECK: vst2.8 {d16[1], d17[1]}, [r0:16] 0x5f 0x05 0xc0 0xf4 -# CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] +# CHECK: vst2.16 {d16[1], d17[1]}, [r0:32] 0x8f 0x09 0xc0 0xf4 # CHECK: vst2.32 {d16[1], d17[1]}, [r0] 0x6f 0x15 0xc0 0xf4 # CHECK: vst2.16 {d17[1], d19[1]}, [r0] 0x5f 0x19 0xc0 0xf4 -# CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] +# CHECK: vst2.32 {d17[0], d19[0]}, [r0:64] 0x2f 0x02 0xc0 0xf4 # CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0] @@ -1879,13 +1879,13 @@ # CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0] 0x3f 0x03 0xc0 0xf4 -# CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +# CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] 0x4f 0x07 0xc0 0xf4 # CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] 0xaf 0x0b 0xc0 0xf4 -# CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +# CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] 0xff 0x17 0xc0 0xf4 -# CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] +# CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] 0x4f 0x1b 0xc0 0xf4 # CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @@ -1920,11 +1920,11 @@ # CHECK: vcvttmi.f32.f16 s2, s19 0x1d 0x76 0x66 0xf4 -# CHECK: vld1.8 {d23, d24, d25}, [r6, :64]! +# CHECK: vld1.8 {d23, d24, d25}, [r6:64]! 0x9d 0x62 0x6f 0xf4 -# CHECK: vld1.32 {d22, d23, d24, d25}, [pc, :64]! +# CHECK: vld1.32 {d22, d23, d24, d25}, [pc:64]! 0x9d 0xaa 0x41 0xf4 -# CHECK: vst1.32 {d26, d27}, [r1, :64]! +# CHECK: vst1.32 {d26, d27}, [r1:64]! 0x10 0x0f 0x83 0xf2 0x50 0x0f 0x83 0xf2 diff --git a/test/MC/Disassembler/ARM/neont-VLD-reencoding.txt b/test/MC/Disassembler/ARM/neont-VLD-reencoding.txt index e53739e739..650614351f 100644 --- a/test/MC/Disassembler/ARM/neont-VLD-reencoding.txt +++ b/test/MC/Disassembler/ARM/neont-VLD-reencoding.txt @@ -28,13 +28,13 @@ 0xa0 0xf9 0xd0 0x04 # CHECK: vld1.16 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x04] -# CHECK: vld1.16 {d0[0]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x10,0x04] +# CHECK: vld1.16 {d0[0]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x10,0x04] # CHECK: vld1.16 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x04] -# CHECK: vld1.16 {d0[1]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x50,0x04] +# CHECK: vld1.16 {d0[1]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x50,0x04] # CHECK: vld1.16 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x04] -# CHECK: vld1.16 {d0[2]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x90,0x04] +# CHECK: vld1.16 {d0[2]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x90,0x04] # CHECK: vld1.16 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x04] -# CHECK: vld1.16 {d0[3]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0xd0,0x04] +# CHECK: vld1.16 {d0[3]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0xd0,0x04] 0xa0 0xf9 0x00 0x08 0xa0 0xf9 0x30 0x08 @@ -42,20 +42,20 @@ 0xa0 0xf9 0xb0 0x08 # CHECK: vld1.32 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x08] -# CHECK: vld1.32 {d0[0]}, [r0, :32], r0 @ encoding: [0xa0,0xf9,0x30,0x08] +# CHECK: vld1.32 {d0[0]}, [r0:32], r0 @ encoding: [0xa0,0xf9,0x30,0x08] # CHECK: vld1.32 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x08] -# CHECK: vld1.32 {d0[1]}, [r0, :32], r0 @ encoding: [0xa0,0xf9,0xb0,0x08] +# CHECK: vld1.32 {d0[1]}, [r0:32], r0 @ encoding: [0xa0,0xf9,0xb0,0x08] 0xa0 0xf9 0x1f 0x04 0xa0 0xf9 0x8f 0x00 -# CHECK: vld1.16 {d0[0]}, [r0, :16] @ encoding: [0xa0,0xf9,0x1f,0x04] +# CHECK: vld1.16 {d0[0]}, [r0:16] @ encoding: [0xa0,0xf9,0x1f,0x04] # CHECK: vld1.8 {d0[4]}, [r0] @ encoding: [0xa0,0xf9,0x8f,0x00] 0xa0 0xf9 0x1d 0x04 0xa0 0xf9 0x8d 0x00 -# CHECK: vld1.16 {d0[0]}, [r0, :16]! @ encoding: [0xa0,0xf9,0x1d,0x04] +# CHECK: vld1.16 {d0[0]}, [r0:16]! @ encoding: [0xa0,0xf9,0x1d,0x04] # CHECK: vld1.8 {d0[4]}, [r0]! @ encoding: [0xa0,0xf9,0x8d,0x00] 0xa5 0xf9 0x10 0x04 @@ -63,15 +63,15 @@ 0xae 0xf9 0x1a 0x04 0xa5 0xf9 0x1a 0x94 -# CHECK: vld1.16 {d0[0]}, [r5, :16], r0 @ encoding: [0xa5,0xf9,0x10,0x04] -# CHECK: vld1.16 {d0[0]}, [r5, :16], r10 @ encoding: [0xa5,0xf9,0x1a,0x04] -# CHECK: vld1.16 {d0[0]}, [lr, :16], r10 @ encoding: [0xae,0xf9,0x1a,0x04] -# CHECK: vld1.16 {d9[0]}, [r5, :16], r10 @ encoding: [0xa5,0xf9,0x1a,0x94] +# CHECK: vld1.16 {d0[0]}, [r5:16], r0 @ encoding: [0xa5,0xf9,0x10,0x04] +# CHECK: vld1.16 {d0[0]}, [r5:16], r10 @ encoding: [0xa5,0xf9,0x1a,0x04] +# CHECK: vld1.16 {d0[0]}, [lr:16], r10 @ encoding: [0xae,0xf9,0x1a,0x04] +# CHECK: vld1.16 {d9[0]}, [r5:16], r10 @ encoding: [0xa5,0xf9,0x1a,0x94] 0xa0 0xf9 0x20 0x0b 0xa0 0xf9 0x20 0x07 0xa0 0xf9 0x20 0x03 -# CHECK: vld4.32 {d0[0], d1[0], d2[0], d3[0]}, [r0, :128], r0 @ encoding: [0xa0,0xf9,0x20,0x0b] +# CHECK: vld4.32 {d0[0], d1[0], d2[0], d3[0]}, [r0:128], r0 @ encoding: [0xa0,0xf9,0x20,0x0b] # CHECK: vld4.16 {d0[0], d2[0], d4[0], d6[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x07] # CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x03] diff --git a/test/MC/Disassembler/ARM/neont-VST-reencoding.txt b/test/MC/Disassembler/ARM/neont-VST-reencoding.txt index eb3722c085..5119d925d8 100644 --- a/test/MC/Disassembler/ARM/neont-VST-reencoding.txt +++ b/test/MC/Disassembler/ARM/neont-VST-reencoding.txt @@ -28,13 +28,13 @@ 0xc9 0xf9 0xd9 0x94 # CHECK: vst1.16 {d0[0]}, [r0], r0 @ encoding: [0x80,0xf9,0x00,0x04] -# CHECK: vst1.16 {d16[0]}, [r3, :16], r3 @ encoding: [0xc3,0xf9,0x13,0x04] +# CHECK: vst1.16 {d16[0]}, [r3:16], r3 @ encoding: [0xc3,0xf9,0x13,0x04] # CHECK: vst1.16 {d16[1]}, [r4], r3 @ encoding: [0xc4,0xf9,0x43,0x04] -# CHECK: vst1.16 {d16[1]}, [r5, :16], r5 @ encoding: [0xc5,0xf9,0x55,0x04] +# CHECK: vst1.16 {d16[1]}, [r5:16], r5 @ encoding: [0xc5,0xf9,0x55,0x04] # CHECK: vst1.16 {d16[2]}, [r6], r5 @ encoding: [0xc6,0xf9,0x85,0x04] -# CHECK: vst1.16 {d23[2]}, [r7, :16], r5 @ encoding: [0xc7,0xf9,0x95,0x74] +# CHECK: vst1.16 {d23[2]}, [r7:16], r5 @ encoding: [0xc7,0xf9,0x95,0x74] # CHECK: vst1.16 {d24[3]}, [r8], r7 @ encoding: [0xc8,0xf9,0xc7,0x84] -# CHECK: vst1.16 {d25[3]}, [r9, :16], r9 @ encoding: [0xc9,0xf9,0xd9,0x94] +# CHECK: vst1.16 {d25[3]}, [r9:16], r9 @ encoding: [0xc9,0xf9,0xd9,0x94] 0x8a 0xf9 0x01 0xa8 0xcb 0xf9 0x32 0x18 @@ -42,20 +42,20 @@ 0xcd 0xf9 0xb4 0x28 # CHECK: vst1.32 {d10[0]}, [r10], r1 @ encoding: [0x8a,0xf9,0x01,0xa8] -# CHECK: vst1.32 {d17[0]}, [r11, :32], r2 @ encoding: [0xcb,0xf9,0x32,0x18] +# CHECK: vst1.32 {d17[0]}, [r11:32], r2 @ encoding: [0xcb,0xf9,0x32,0x18] # CHECK: vst1.32 {d11[1]}, [r12], r3 @ encoding: [0x8c,0xf9,0x83,0xb8] -# CHECK: vst1.32 {d18[1]}, [sp, :32], r4 @ encoding: [0xcd,0xf9,0xb4,0x28] +# CHECK: vst1.32 {d18[1]}, [sp:32], r4 @ encoding: [0xcd,0xf9,0xb4,0x28] 0x81 0xf9 0x1f 0x44 0x82 0xf9 0x8f 0x30 -# CHECK: vst1.16 {d4[0]}, [r1, :16] @ encoding: [0x81,0xf9,0x1f,0x44] +# CHECK: vst1.16 {d4[0]}, [r1:16] @ encoding: [0x81,0xf9,0x1f,0x44] # CHECK: vst1.8 {d3[4]}, [r2] @ encoding: [0x82,0xf9,0x8f,0x30] 0x83 0xf9 0x1d 0x24 0x84 0xf9 0x8d 0x10 -# CHECK: vst1.16 {d2[0]}, [r3, :16]! @ encoding: [0x83,0xf9,0x1d,0x24] +# CHECK: vst1.16 {d2[0]}, [r3:16]! @ encoding: [0x83,0xf9,0x1d,0x24] # CHECK: vst1.8 {d1[4]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x10] 0x85 0xf9 0x10 0x04 @@ -63,15 +63,15 @@ 0x8e 0xf9 0x1a 0x84 0x85 0xf9 0x1a 0x94 -# CHECK: vst1.16 {d0[0]}, [r5, :16], r0 @ encoding: [0x85,0xf9,0x10,0x04] -# CHECK: vst1.16 {d7[0]}, [r5, :16], r10 @ encoding: [0x85,0xf9,0x1a,0x74] -# CHECK: vst1.16 {d8[0]}, [lr, :16], r10 @ encoding: [0x8e,0xf9,0x1a,0x84] -# CHECK: vst1.16 {d9[0]}, [r5, :16], r10 @ encoding: [0x85,0xf9,0x1a,0x94] +# CHECK: vst1.16 {d0[0]}, [r5:16], r0 @ encoding: [0x85,0xf9,0x10,0x04] +# CHECK: vst1.16 {d7[0]}, [r5:16], r10 @ encoding: [0x85,0xf9,0x1a,0x74] +# CHECK: vst1.16 {d8[0]}, [lr:16], r10 @ encoding: [0x8e,0xf9,0x1a,0x84] +# CHECK: vst1.16 {d9[0]}, [r5:16], r10 @ encoding: [0x85,0xf9,0x1a,0x94] 0x81 0xf9 0x24 0x0b 0x82 0xf9 0x25 0x07 0x83 0xf9 0x26 0x03 -# CHECK: vst4.32 {d0[0], d1[0], d2[0], d3[0]}, [r1, :128], r4 @ encoding: [0x81,0xf9,0x24,0x0b] +# CHECK: vst4.32 {d0[0], d1[0], d2[0], d3[0]}, [r1:128], r4 @ encoding: [0x81,0xf9,0x24,0x0b] # CHECK: vst4.16 {d0[0], d2[0], d4[0], d6[0]}, [r2], r5 @ encoding: [0x82,0xf9,0x25,0x07] # CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r3], r6 @ encoding: [0x83,0xf9,0x26,0x03] diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt index 7d7010febb..3374578472 100644 --- a/test/MC/Disassembler/ARM/neont2.txt +++ b/test/MC/Disassembler/ARM/neont2.txt @@ -1379,7 +1379,7 @@ # CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 0x60 0xf9 0x1f 0x07 -# CHECK: vld1.8 {d16}, [r0, :64] +# CHECK: vld1.8 {d16}, [r0:64] 0x60 0xf9 0x4f 0x07 # CHECK: vld1.16 {d16}, [r0] 0x60 0xf9 0x8f 0x07 @@ -1387,37 +1387,37 @@ 0x60 0xf9 0xcf 0x07 # CHECK: vld1.64 {d16}, [r0] 0x60 0xf9 0x1f 0x0a -# CHECK: vld1.8 {d16, d17}, [r0, :64] +# CHECK: vld1.8 {d16, d17}, [r0:64] 0x60 0xf9 0x6f 0x0a -# CHECK: vld1.16 {d16, d17}, [r0, :128] +# CHECK: vld1.16 {d16, d17}, [r0:128] 0x60 0xf9 0x8f 0x0a # CHECK: vld1.32 {d16, d17}, [r0] 0x60 0xf9 0xcf 0x0a # CHECK: vld1.64 {d16, d17}, [r0] 0x60 0xf9 0x1f 0x08 -# CHECK: vld2.8 {d16, d17}, [r0, :64] +# CHECK: vld2.8 {d16, d17}, [r0:64] 0x60 0xf9 0x6f 0x08 -# CHECK: vld2.16 {d16, d17}, [r0, :128] +# CHECK: vld2.16 {d16, d17}, [r0:128] 0x60 0xf9 0x8f 0x08 # CHECK: vld2.32 {d16, d17}, [r0] 0x60 0xf9 0x1f 0x03 -# CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64] 0x60 0xf9 0x6f 0x03 -# CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128] 0x60 0xf9 0xbf 0x03 -# CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] +# CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256] 0x60 0xf9 0x1f 0x04 -# CHECK: vld3.8 {d16, d17, d18}, [r0, :64] +# CHECK: vld3.8 {d16, d17, d18}, [r0:64] 0x60 0xf9 0x4f 0x04 # CHECK: vld3.16 {d16, d17, d18}, [r0] 0x60 0xf9 0x8f 0x04 # CHECK: vld3.32 {d16, d17, d18}, [r0] 0x60 0xf9 0x1d 0x05 -# CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! +# CHECK: vld3.8 {d16, d18, d20}, [r0:64]! 0x60 0xf9 0x1d 0x15 -# CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! +# CHECK: vld3.8 {d17, d19, d21}, [r0:64]! 0x60 0xf9 0x4d 0x05 # CHECK: vld3.16 {d16, d18, d20}, [r0]! 0x60 0xf9 0x4d 0x15 @@ -1428,15 +1428,15 @@ # CHECK: vld3.32 {d17, d19, d21}, [r0]! 0x60 0xf9 0x1f 0x00 -# CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64] 0x60 0xf9 0x6f 0x00 -# CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128] 0x60 0xf9 0xbf 0x00 -# CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] +# CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256] 0x60 0xf9 0x3d 0x01 -# CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! +# CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]! 0x60 0xf9 0x3d 0x11 -# CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! +# CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]! 0x60 0xf9 0x4d 0x01 # CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! 0x60 0xf9 0x4d 0x11 @@ -1449,20 +1449,20 @@ 0xe0 0xf9 0x6f 0x00 # CHECK: vld1.8 {d16[3]}, [r0] 0xe0 0xf9 0x9f 0x04 -# CHECK: vld1.16 {d16[2]}, [r0, :16] +# CHECK: vld1.16 {d16[2]}, [r0:16] 0xe0 0xf9 0xbf 0x08 -# CHECK: vld1.32 {d16[1]}, [r0, :32] +# CHECK: vld1.32 {d16[1]}, [r0:32] 0xe0 0xf9 0x3f 0x01 -# CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] +# CHECK: vld2.8 {d16[1], d17[1]}, [r0:16] 0xe0 0xf9 0x5f 0x05 -# CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] +# CHECK: vld2.16 {d16[1], d17[1]}, [r0:32] 0xe0 0xf9 0x8f 0x09 # CHECK: vld2.32 {d16[1], d17[1]}, [r0] 0xe0 0xf9 0x6f 0x15 # CHECK: vld2.16 {d17[1], d19[1]}, [r0] 0xe0 0xf9 0x5f 0x19 -# CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] +# CHECK: vld2.32 {d17[0], d19[0]}, [r0:64] 0xe0 0xf9 0x2f 0x02 # CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] @@ -1495,43 +1495,43 @@ # CHECK: vld3.32 {d0[], d2[], d4[]}, [r4], r5 0xe0 0xf9 0x3f 0x03 -# CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +# CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] 0xe0 0xf9 0x4f 0x07 # CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] 0xe0 0xf9 0xaf 0x0b -# CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +# CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] 0xe0 0xf9 0x7f 0x07 -# CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] +# CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64] 0xe0 0xf9 0x4f 0x1b # CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] 0xa4 0xf9 0x0f 0x0f # CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4] 0xa4 0xf9 0x3f 0x0f -# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32] +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32] 0xa4 0xf9 0x1d 0x0f -# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4, :32]! +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! 0xa4 0xf9 0x35 0x0f -# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32], r5 +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r5 0xa4 0xf9 0x4f 0x0f # CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4] 0xa4 0xf9 0x7f 0x0f -# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64] +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64] 0xa4 0xf9 0x5d 0x0f -# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4, :64]! +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! 0xa4 0xf9 0x75 0x0f -# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64], r5 +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r5 0xa4 0xf9 0x8f 0x0f # CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4] 0xa4 0xf9 0xbf 0x0f -# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :64] +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64] 0xa4 0xf9 0xdd 0x0f -# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4, :128]! +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]! 0xa4 0xf9 0xf5 0x0f -# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :128], r5 +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r5 0x40 0xf9 0x1f 0x07 -# CHECK: vst1.8 {d16}, [r0, :64] +# CHECK: vst1.8 {d16}, [r0:64] 0x40 0xf9 0x4f 0x07 # CHECK: vst1.16 {d16}, [r0] 0x40 0xf9 0x8f 0x07 @@ -1539,37 +1539,37 @@ 0x40 0xf9 0xcf 0x07 # CHECK: vst1.64 {d16}, [r0] 0x40 0xf9 0x1f 0x0a -# CHECK: vst1.8 {d16, d17}, [r0, :64] +# CHECK: vst1.8 {d16, d17}, [r0:64] 0x40 0xf9 0x6f 0x0a -# CHECK: vst1.16 {d16, d17}, [r0, :128] +# CHECK: vst1.16 {d16, d17}, [r0:128] 0x40 0xf9 0x8f 0x0a # CHECK: vst1.32 {d16, d17}, [r0] 0x40 0xf9 0xcf 0x0a # CHECK: vst1.64 {d16, d17}, [r0] 0x40 0xf9 0x1f 0x08 -# CHECK: vst2.8 {d16, d17}, [r0, :64] +# CHECK: vst2.8 {d16, d17}, [r0:64] 0x40 0xf9 0x6f 0x08 -# CHECK: vst2.16 {d16, d17}, [r0, :128] +# CHECK: vst2.16 {d16, d17}, [r0:128] 0x40 0xf9 0x8f 0x08 # CHECK: vst2.32 {d16, d17}, [r0] 0x40 0xf9 0x1f 0x03 -# CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64] 0x40 0xf9 0x6f 0x03 -# CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128] 0x40 0xf9 0xbf 0x03 -# CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] +# CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256] 0x40 0xf9 0x1f 0x04 -# CHECK: vst3.8 {d16, d17, d18}, [r0, :64] +# CHECK: vst3.8 {d16, d17, d18}, [r0:64] 0x40 0xf9 0x4f 0x04 # CHECK: vst3.16 {d16, d17, d18}, [r0] 0x40 0xf9 0x8f 0x04 # CHECK: vst3.32 {d16, d17, d18}, [r0] 0x40 0xf9 0x1d 0x05 -# CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! +# CHECK: vst3.8 {d16, d18, d20}, [r0:64]! 0x40 0xf9 0x1d 0x15 -# CHECK: vst3.8 {d17, d19, d21}, [r0, :64]! +# CHECK: vst3.8 {d17, d19, d21}, [r0:64]! 0x40 0xf9 0x4d 0x05 # CHECK: vst3.16 {d16, d18, d20}, [r0]! 0x40 0xf9 0x4d 0x15 @@ -1580,13 +1580,13 @@ # CHECK: vst3.32 {d17, d19, d21}, [r0]! 0x40 0xf9 0x1f 0x00 -# CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64] 0x40 0xf9 0x6f 0x00 -# CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128] 0x40 0xf9 0x3d 0x01 -# CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! +# CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]! 0x40 0xf9 0x3d 0x11 -# CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]! +# CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]! 0x40 0xf9 0x4d 0x01 # CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! 0x40 0xf9 0x4d 0x11 @@ -1597,15 +1597,15 @@ # CHECK: vst4.32 {d17, d19, d21, d23}, [r0]! 0xc0 0xf9 0x3f 0x01 -# CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] +# CHECK: vst2.8 {d16[1], d17[1]}, [r0:16] 0xc0 0xf9 0x5f 0x05 -# CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] +# CHECK: vst2.16 {d16[1], d17[1]}, [r0:32] 0xc0 0xf9 0x8f 0x09 # CHECK: vst2.32 {d16[1], d17[1]}, [r0] 0xc0 0xf9 0x6f 0x15 # CHECK: vst2.16 {d17[1], d19[1]}, [r0] 0xc0 0xf9 0x5f 0x19 -# CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] +# CHECK: vst2.32 {d17[0], d19[0]}, [r0:64] 0xc0 0xf9 0x2f 0x02 # CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0] @@ -1619,26 +1619,26 @@ # CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0] 0xc0 0xf9 0x3f 0x03 -# CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +# CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] 0xc0 0xf9 0x4f 0x07 # CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] 0xc0 0xf9 0xaf 0x0b -# CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +# CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] 0xc0 0xf9 0xff 0x17 -# CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] +# CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] 0xc0 0xf9 0x4f 0x1b # CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] 0x63 0xf9 0x37 0xc9 -# CHECK: vld2.8 {d28, d30}, [r3, :256], r7 +# CHECK: vld2.8 {d28, d30}, [r3:256], r7 # rdar://10798451 0xe7 0xf9 0x32 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2 +# CHECK vld2.8 {d17[], d19[]}, [r7:16], r2 0xe7 0xf9 0x3d 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16]! +# CHECK vld2.8 {d17[], d19[]}, [r7:16]! 0xe7 0xf9 0x3f 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16] +# CHECK vld2.8 {d17[], d19[]}, [r7:16] # rdar://11034702 0x04 0xf9 0x0d 0x87 @@ -2046,9 +2046,9 @@ # rdar://10798451 0xe7 0xf9 0x32 0x1d -# CHECK: vld2.8 {d17[], d19[]}, [r7, :16], r2 +# CHECK: vld2.8 {d17[], d19[]}, [r7:16], r2 0xe7 0xf9 0x3d 0x1d -# CHECK: vld2.8 {d17[], d19[]}, [r7, :16]! +# CHECK: vld2.8 {d17[], d19[]}, [r7:16]! 0xe7 0xf9 0x3f 0x1d -# CHECK: vld2.8 {d17[], d19[]}, [r7, :16] +# CHECK: vld2.8 {d17[], d19[]}, [r7:16] |