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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-18 17:13:57 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-18 17:13:57 +0000 |
commit | 2b6e6fc1a8c188a9ccbe028b42697d32edaa2a1c (patch) | |
tree | e5d58b567d8d04b6c61c263bbf350b5f494e6334 /test | |
parent | 795ae8615f20eb5b55e15b8eeca9c909ef78a8f0 (diff) | |
download | llvm-2b6e6fc1a8c188a9ccbe028b42697d32edaa2a1c.tar.gz llvm-2b6e6fc1a8c188a9ccbe028b42697d32edaa2a1c.tar.bz2 llvm-2b6e6fc1a8c188a9ccbe028b42697d32edaa2a1c.tar.xz |
R600/SI: Add intrinsics for brev instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211187 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/R600/llvm.AMDGPU.brev.ll | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/test/CodeGen/R600/llvm.AMDGPU.brev.ll b/test/CodeGen/R600/llvm.AMDGPU.brev.ll new file mode 100644 index 0000000000..68a5ad0649 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.brev.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s + +declare i32 @llvm.AMDGPU.brev(i32) nounwind readnone + +; FUNC-LABEL: @s_brev_i32: +; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], +; SI: S_BREV_B32 [[SRESULT:s[0-9]+]], [[VAL]] +; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] +; SI: BUFFER_STORE_DWORD [[VRESULT]], +; SI: S_ENDPGM +define void @s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { + %ctlz = call i32 @llvm.AMDGPU.brev(i32 %val) nounwind readnone + store i32 %ctlz, i32 addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: @v_brev_i32: +; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], +; SI: V_BFREV_B32_e32 [[RESULT:v[0-9]+]], [[VAL]] +; SI: BUFFER_STORE_DWORD [[RESULT]], +; SI: S_ENDPGM +define void @v_brev_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { + %val = load i32 addrspace(1)* %valptr, align 4 + %ctlz = call i32 @llvm.AMDGPU.brev(i32 %val) nounwind readnone + store i32 %ctlz, i32 addrspace(1)* %out, align 4 + ret void +} |