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| author | Evan Cheng <evan.cheng@apple.com> | 2011-11-08 21:21:09 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-11-08 21:21:09 +0000 |
| commit | 3568a1051efb9a9edbd4914b04b44e9d7bc1b004 (patch) | |
| tree | 871918870b9c3a8712b540a382dc734b5a65a83d /test | |
| parent | 66dc8ca04b719f3ab4aa650609dbd56b055ecb34 (diff) | |
| download | llvm-3568a1051efb9a9edbd4914b04b44e9d7bc1b004.tar.gz llvm-3568a1051efb9a9edbd4914b04b44e9d7bc1b004.tar.bz2 llvm-3568a1051efb9a9edbd4914b04b44e9d7bc1b004.tar.xz | |
Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144123 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/ldrd.ll | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll index 8010f20689..d72e9bfc1d 100644 --- a/test/CodeGen/ARM/ldrd.ll +++ b/test/CodeGen/ARM/ldrd.ll @@ -1,21 +1,22 @@ -; RUN: llc < %s -mtriple=armv6-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V6 -; RUN: llc < %s -mtriple=armv5-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V5 -; RUN: llc < %s -mtriple=armv6-eabi -regalloc=linearscan | FileCheck %s -check-prefix=EABI -; rdar://r6949835 +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=fast | FileCheck %s -check-prefix=A8 +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 -regalloc=fast | FileCheck %s -check-prefix=M3 +; rdar://6949835 -; Magic ARM pair hints works best with linearscan. +; Magic ARM pair hints works best with linearscan / fast. + +; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base +; register when interrupted or faulted. @b = external global i64* define i64 @t(i64 %a) nounwind readonly { entry: -;V6: ldrd r2, r3, [r2] - -;V5: ldr r{{[0-9]+}}, [r2] -;V5: ldr r{{[0-9]+}}, [r2, #4] +; A8: t: +; A8: ldrd r2, r3, [r2] -;EABI: ldr r{{[0-9]+}}, [r2] -;EABI: ldr r{{[0-9]+}}, [r2, #4] +; M3: t: +; M3-NOT: ldrd +; M3: ldm.w r2, {r2, r3} %0 = load i64** @b, align 4 %1 = load i64* %0, align 4 |