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| author | Silviu Baranga <silviu.baranga@arm.com> | 2012-11-29 14:41:25 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-11-29 14:41:25 +0000 |
| commit | 35b3df6e31f9aac70fb471d74e39f899dfbd689f (patch) | |
| tree | 49a621823b33ca74be2e4c751d693e5223490bf0 /test | |
| parent | 5175fd990c898a49708d60b84e7838bead48f2cd (diff) | |
| download | llvm-35b3df6e31f9aac70fb471d74e39f899dfbd689f.tar.gz llvm-35b3df6e31f9aac70fb471d74e39f899dfbd689f.tar.bz2 llvm-35b3df6e31f9aac70fb471d74e39f899dfbd689f.tar.xz | |
Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168886 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/atomic-64bit.ll | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/atomic-64bit.ll b/test/CodeGen/ARM/atomic-64bit.ll index be51e3c129..69da6221b7 100644 --- a/test/CodeGen/ARM/atomic-64bit.ll +++ b/test/CodeGen/ARM/atomic-64bit.ll @@ -126,3 +126,64 @@ define void @test9(i64* %ptr, i64 %val) { store atomic i64 %val, i64* %ptr seq_cst, align 8 ret void } + +define i64 @test10(i64* %ptr, i64 %val) { +; CHECK: test10: +; CHECK: dmb ish +; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] +; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]] +; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]] +; CHECK: ble +; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]] +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw min i64* %ptr, i64 %val seq_cst + ret i64 %r +} + +define i64 @test11(i64* %ptr, i64 %val) { +; CHECK: test11: +; CHECK: dmb ish +; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] +; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]] +; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]] +; CHECK: bls +; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]] +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw umin i64* %ptr, i64 %val seq_cst + ret i64 %r +} + +define i64 @test12(i64* %ptr, i64 %val) { +; CHECK: test12: +; CHECK: dmb ish +; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] +; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]] +; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]] +; CHECK: bge +; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]] +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw max i64* %ptr, i64 %val seq_cst + ret i64 %r +} + +define i64 @test13(i64* %ptr, i64 %val) { +; CHECK: test13: +; CHECK: dmb ish +; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] +; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]] +; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]] +; CHECK: bhs +; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]] +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw umax i64* %ptr, i64 %val seq_cst + ret i64 %r +} + |