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authorJim Grosbach <grosbach@apple.com>2013-08-26 20:22:05 +0000
committerJim Grosbach <grosbach@apple.com>2013-08-26 20:22:05 +0000
commit383a810b129aa5120d6a7f6e88e141ec4a45f61b (patch)
tree5a9f19d6f84b1995b5419b10e12b600c536c45a0 /test
parent7c42ede04579373a2d3e124b4417d89430d541f3 (diff)
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ARM: Constrain regclass for TSTri instruction.
Get the register class right for the TST instruction. This keeps the machine verifier happy, enabling us to turn it on for another test. rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189274 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/ARM/fast-isel-br-phi.ll2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/fast-isel-br-phi.ll b/test/CodeGen/ARM/fast-isel-br-phi.ll
index a0aba694e4..3b9d4652b7 100644
--- a/test/CodeGen/ARM/fast-isel-br-phi.ll
+++ b/test/CodeGen/ARM/fast-isel-br-phi.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios
; This test ensures HandlePHINodesInSuccessorBlocks() is able to promote basic
; non-legal integer types (i.e., i1, i8, i16).