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author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-12-11 14:31:04 +0000 |
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committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-12-11 14:31:04 +0000 |
commit | 3bf51cf30293272198515bfe315db1dd81d86e63 (patch) | |
tree | 0a3e64b437636a4ac69b8bdfd924591283159199 /test | |
parent | e54c1060a6a3f2a30b26c3289c08ae1bc8a845b9 (diff) | |
download | llvm-3bf51cf30293272198515bfe315db1dd81d86e63.tar.gz llvm-3bf51cf30293272198515bfe315db1dd81d86e63.tar.bz2 llvm-3bf51cf30293272198515bfe315db1dd81d86e63.tar.xz |
AVX-512: Removed "z" suffix from AVX-512 instructions, since it is incompatible with GCC.
I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll
I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197041 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/X86/avx512-arith.ll | 8 | ||||
-rw-r--r-- | test/CodeGen/X86/avx512-cmp.ll | 6 | ||||
-rw-r--r-- | test/CodeGen/X86/avx512-cvt.ll | 30 | ||||
-rw-r--r-- | test/CodeGen/X86/avx512-insert-extract.ll | 10 | ||||
-rw-r--r-- | test/CodeGen/X86/avx512-intrinsics.ll | 22 | ||||
-rw-r--r-- | test/CodeGen/X86/avx512-mov.ll | 32 | ||||
-rw-r--r-- | test/CodeGen/X86/avx512-shuffle.ll | 6 | ||||
-rw-r--r-- | test/CodeGen/X86/avx512-vbroadcast-crash.ll | 11 | ||||
-rw-r--r-- | test/CodeGen/X86/avx512-vbroadcast.ll | 19 |
9 files changed, 72 insertions, 72 deletions
diff --git a/test/CodeGen/X86/avx512-arith.ll b/test/CodeGen/X86/avx512-arith.ll index e27600ecd7..223c023a8a 100644 --- a/test/CodeGen/X86/avx512-arith.ll +++ b/test/CodeGen/X86/avx512-arith.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s ; CHECK-LABEL: addpd512 ; CHECK: vaddpd @@ -196,7 +196,7 @@ define <16 x i32> @vpmulld_test(<16 x i32> %i, <16 x i32> %j) { } ; CHECK-LABEL: sqrtA -; CHECK: vsqrtssz +; CHECK: vsqrtss {{.*}} encoding: [0x62 ; CHECK: ret declare float @sqrtf(float) readnone define float @sqrtA(float %a) nounwind uwtable readnone ssp { @@ -206,7 +206,7 @@ entry: } ; CHECK-LABEL: sqrtB -; CHECK: vsqrtsdz +; CHECK: vsqrtsd {{.*}}## encoding: [0x62 ; CHECK: ret declare double @sqrt(double) readnone define double @sqrtB(double %a) nounwind uwtable readnone ssp { @@ -216,7 +216,7 @@ entry: } ; CHECK-LABEL: sqrtC -; CHECK: vsqrtssz +; CHECK: vsqrtss {{.*}}## encoding: [0x62 ; CHECK: ret declare float @llvm.sqrt.f32(float) define float @sqrtC(float %a) nounwind { diff --git a/test/CodeGen/X86/avx512-cmp.ll b/test/CodeGen/X86/avx512-cmp.ll index ba52745e6c..5201e32f57 100644 --- a/test/CodeGen/X86/avx512-cmp.ll +++ b/test/CodeGen/X86/avx512-cmp.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding | FileCheck %s -; CHECK: vucomisdz +; CHECK: vucomisd {{.*}}encoding: [0x62 define double @test1(double %a, double %b) nounwind { %tobool = fcmp une double %a, %b br i1 %tobool, label %l1, label %l2 @@ -13,7 +13,7 @@ l2: ret double %c1 } -; CHECK: vucomissz +; CHECK: vucomiss {{.*}}encoding: [0x62 define float @test2(float %a, float %b) nounwind { %tobool = fcmp olt float %a, %b br i1 %tobool, label %l1, label %l2 diff --git a/test/CodeGen/X86/avx512-cvt.ll b/test/CodeGen/X86/avx512-cvt.ll index ed68ff7bcb..89a69e7b98 100644 --- a/test/CodeGen/X86/avx512-cvt.ll +++ b/test/CodeGen/X86/avx512-cvt.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding | FileCheck %s ; CHECK-LABEL: sitof32 ; CHECK: vcvtdq2ps %zmm @@ -67,7 +67,7 @@ define <8 x double> @fpext00(<8 x float> %b) nounwind { } ; CHECK-LABEL: funcA -; CHECK: vcvtsi2sdqz (% +; CHECK: vcvtsi2sdq (%rdi){{.*}} encoding: [0x62 ; CHECK: ret define double @funcA(i64* nocapture %e) { entry: @@ -77,7 +77,7 @@ entry: } ; CHECK-LABEL: funcB -; CHECK: vcvtsi2sdlz (% +; CHECK: vcvtsi2sdl (%{{.*}} encoding: [0x62 ; CHECK: ret define double @funcB(i32* %e) { entry: @@ -87,7 +87,7 @@ entry: } ; CHECK-LABEL: funcC -; CHECK: vcvtsi2sslz (% +; CHECK: vcvtsi2ssl (%{{.*}} encoding: [0x62 ; CHECK: ret define float @funcC(i32* %e) { entry: @@ -97,7 +97,7 @@ entry: } ; CHECK-LABEL: i64tof32 -; CHECK: vcvtsi2ssqz (% +; CHECK: vcvtsi2ssq (%{{.*}} encoding: [0x62 ; CHECK: ret define float @i64tof32(i64* %e) { entry: @@ -107,7 +107,7 @@ entry: } ; CHECK-LABEL: fpext -; CHECK: vcvtss2sdz +; CHECK: vcvtss2sd {{.*}} encoding: [0x62 ; CHECK: ret define void @fpext() { entry: @@ -120,9 +120,9 @@ entry: } ; CHECK-LABEL: fpround_scalar -; CHECK: vmovsdz -; CHECK: vcvtsd2ssz -; CHECK: vmovssz +; CHECK: vmovsd {{.*}} encoding: [0x62 +; CHECK: vcvtsd2ss {{.*}} encoding: [0x62 +; CHECK: vmovss {{.*}} encoding: [0x62 ; CHECK: ret define void @fpround_scalar() nounwind uwtable { entry: @@ -135,7 +135,7 @@ entry: } ; CHECK-LABEL: long_to_double -; CHECK: vmovqz +; CHECK: vmovq {{.*}} encoding: [0x62 ; CHECK: ret define double @long_to_double(i64 %x) { %res = bitcast i64 %x to double @@ -143,7 +143,7 @@ define double @long_to_double(i64 %x) { } ; CHECK-LABEL: double_to_long -; CHECK: vmovqz +; CHECK: vmovq {{.*}} encoding: [0x62 ; CHECK: ret define i64 @double_to_long(double %x) { %res = bitcast double %x to i64 @@ -151,7 +151,7 @@ define i64 @double_to_long(double %x) { } ; CHECK-LABEL: int_to_float -; CHECK: vmovdz +; CHECK: vmovd {{.*}} encoding: [0x62 ; CHECK: ret define float @int_to_float(i32 %x) { %res = bitcast i32 %x to float @@ -159,7 +159,7 @@ define float @int_to_float(i32 %x) { } ; CHECK-LABEL: float_to_int -; CHECK: vmovdz +; CHECK: vmovd {{.*}} encoding: [0x62 ; CHECK: ret define i32 @float_to_int(float %x) { %res = bitcast float %x to i32 @@ -185,7 +185,7 @@ define <16 x float> @uitof32(<16 x i32> %a) nounwind { } ; CHECK-LABEL: @fptosi02 -; CHECK vcvttss2siz +; CHECK vcvttss2si {{.*}} encoding: [0x62 ; CHECK: ret define i32 @fptosi02(float %a) nounwind { %b = fptosi float %a to i32 @@ -193,7 +193,7 @@ define i32 @fptosi02(float %a) nounwind { } ; CHECK-LABEL: @fptoui02 -; CHECK vcvttss2usiz +; CHECK vcvttss2usi {{.*}} encoding: [0x62 ; CHECK: ret define i32 @fptoui02(float %a) nounwind { %b = fptoui float %a to i32 diff --git a/test/CodeGen/X86/avx512-insert-extract.ll b/test/CodeGen/X86/avx512-insert-extract.ll index 3f067401ed..ef6359b4d9 100644 --- a/test/CodeGen/X86/avx512-insert-extract.ll +++ b/test/CodeGen/X86/avx512-insert-extract.ll @@ -44,7 +44,7 @@ define <8 x i64> @test4(<8 x i64> %x) nounwind { } ;CHECK-LABEL: test5: -;CHECK: vextractpsz +;CHECK: vextractps ;CHECK: ret define i32 @test5(<4 x float> %x) nounwind { %ef = extractelement <4 x float> %x, i32 3 @@ -53,7 +53,7 @@ define i32 @test5(<4 x float> %x) nounwind { } ;CHECK-LABEL: test6: -;CHECK: vextractpsz {{.*}}, (%rdi) +;CHECK: vextractps {{.*}}, (%rdi) ;CHECK: ret define void @test6(<4 x float> %x, float* %out) nounwind { %ef = extractelement <4 x float> %x, i32 3 @@ -62,7 +62,7 @@ define void @test6(<4 x float> %x, float* %out) nounwind { } ;CHECK-LABEL: test7 -;CHECK: vmovdz +;CHECK: vmovd ;CHECK: vpermps %zmm ;CHECK: ret define float @test7(<16 x float> %x, i32 %ind) nounwind { @@ -71,7 +71,7 @@ define float @test7(<16 x float> %x, i32 %ind) nounwind { } ;CHECK-LABEL: test8 -;CHECK: vmovqz +;CHECK: vmovq ;CHECK: vpermpd %zmm ;CHECK: ret define double @test8(<8 x double> %x, i32 %ind) nounwind { @@ -89,7 +89,7 @@ define float @test9(<8 x float> %x, i32 %ind) nounwind { } ;CHECK-LABEL: test10 -;CHECK: vmovdz +;CHECK: vmovd ;CHECK: vpermd %zmm ;CHEKK: vmovdz %xmm0, %eax ;CHECK: ret diff --git a/test/CodeGen/X86/avx512-intrinsics.ll b/test/CodeGen/X86/avx512-intrinsics.ll index cd67cd823e..883acb404e 100644 --- a/test/CodeGen/X86/avx512-intrinsics.ll +++ b/test/CodeGen/X86/avx512-intrinsics.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s declare i32 @llvm.x86.avx512.kortestz.w(i16, i16) nounwind readnone ; CHECK-LABEL: test_kortestz @@ -147,42 +147,42 @@ define <16 x float> @test_sqrt_ps_512(<16 x float> %a0) { declare <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float>) nounwind readnone define <4 x float> @test_sqrt_ss(<4 x float> %a0, <4 x float> %a1) { - ; CHECK: vsqrtssz + ; CHECK: vsqrtss {{.*}}encoding: [0x62 %res = call <4 x float> @llvm.x86.avx512.sqrt.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] ret <4 x float> %res } declare <4 x float> @llvm.x86.avx512.sqrt.ss(<4 x float>, <4 x float>) nounwind readnone define <2 x double> @test_sqrt_sd(<2 x double> %a0, <2 x double> %a1) { - ; CHECK: vsqrtsdz + ; CHECK: vsqrtsd {{.*}}encoding: [0x62 %res = call <2 x double> @llvm.x86.avx512.sqrt.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] ret <2 x double> %res } declare <2 x double> @llvm.x86.avx512.sqrt.sd(<2 x double>, <2 x double>) nounwind readnone define i64 @test_x86_sse2_cvtsd2si64(<2 x double> %a0) { - ; CHECK: vcvtsd2siz + ; CHECK: vcvtsd2si {{.*}}encoding: [0x62 %res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0) ; <i64> [#uses=1] ret i64 %res } declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone define <2 x double> @test_x86_sse2_cvtsi642sd(<2 x double> %a0, i64 %a1) { - ; CHECK: vcvtsi2sdqz + ; CHECK: vcvtsi2sdq {{.*}}encoding: [0x62 %res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1] ret <2 x double> %res } declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone define <2 x double> @test_x86_avx512_cvtusi642sd(<2 x double> %a0, i64 %a1) { - ; CHECK: vcvtusi2sdqz + ; CHECK: vcvtusi2sdq {{.*}}encoding: [0x62 %res = call <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1] ret <2 x double> %res } declare <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double>, i64) nounwind readnone define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) { - ; CHECK: vcvttsd2siz + ; CHECK: vcvttsd2si {{.*}}encoding: [0x62 %res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1] ret i64 %res } @@ -190,7 +190,7 @@ declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone define i64 @test_x86_sse_cvtss2si64(<4 x float> %a0) { - ; CHECK: vcvtss2siz + ; CHECK: vcvtss2si {{.*}}encoding: [0x62 %res = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %a0) ; <i64> [#uses=1] ret i64 %res } @@ -198,7 +198,7 @@ declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) nounwind readnone define <4 x float> @test_x86_sse_cvtsi642ss(<4 x float> %a0, i64 %a1) { - ; CHECK: vcvtsi2ssqz + ; CHECK: vcvtsi2ssq {{.*}}encoding: [0x62 %res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1) ; <<4 x float>> [#uses=1] ret <4 x float> %res } @@ -206,14 +206,14 @@ declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone define i64 @test_x86_sse_cvttss2si64(<4 x float> %a0) { - ; CHECK: vcvttss2siz + ; CHECK: vcvttss2si {{.*}}encoding: [0x62 %res = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0) ; <i64> [#uses=1] ret i64 %res } declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone define i64 @test_x86_avx512_cvtsd2usi64(<2 x double> %a0) { - ; CHECK: vcvtsd2usiz + ; CHECK: vcvtsd2usi {{.*}}encoding: [0x62 %res = call i64 @llvm.x86.avx512.cvtsd2usi64(<2 x double> %a0) ; <i64> [#uses=1] ret i64 %res } diff --git a/test/CodeGen/X86/avx512-mov.ll b/test/CodeGen/X86/avx512-mov.ll index 91242b1cc1..13e6843244 100644 --- a/test/CodeGen/X86/avx512-mov.ll +++ b/test/CodeGen/X86/avx512-mov.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s +; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s ; CHECK-LABEL: @test1 -; CHECK: vmovdz %xmm0, %eax +; CHECK: vmovd %xmm0, %eax ## encoding: [0x62 ; CHECK: ret define i32 @test1(float %x) { %res = bitcast float %x to i32 @@ -9,7 +9,7 @@ define i32 @test1(float %x) { } ; CHECK-LABEL: @test2 -; CHECK: vmovdz %edi +; CHECK: vmovd %edi, %xmm0 ## encoding: [0x62 ; CHECK: ret define <4 x i32> @test2(i32 %x) { %res = insertelement <4 x i32>undef, i32 %x, i32 0 @@ -17,7 +17,7 @@ define <4 x i32> @test2(i32 %x) { } ; CHECK-LABEL: @test3 -; CHECK: vmovqz %rdi +; CHECK: vmovq %rdi, %xmm0 ## encoding: [0x62 ; CHECK: ret define <2 x i64> @test3(i64 %x) { %res = insertelement <2 x i64>undef, i64 %x, i32 0 @@ -25,7 +25,7 @@ define <2 x i64> @test3(i64 %x) { } ; CHECK-LABEL: @test4 -; CHECK: vmovdz (%rdi) +; CHECK: vmovd (%rdi), %xmm0 ## encoding: [0x62 ; CHECK: ret define <4 x i32> @test4(i32* %x) { %y = load i32* %x @@ -34,7 +34,7 @@ define <4 x i32> @test4(i32* %x) { } ; CHECK-LABEL: @test5 -; CHECK: vmovssz %xmm0, (%rdi) +; CHECK: vmovss %xmm0, (%rdi) ## encoding: [0x62 ; CHECK: ret define void @test5(float %x, float* %y) { store float %x, float* %y, align 4 @@ -42,7 +42,7 @@ define void @test5(float %x, float* %y) { } ; CHECK-LABEL: @test6 -; CHECK: vmovsdz %xmm0, (%rdi) +; CHECK: vmovsd %xmm0, (%rdi) ## encoding: [0x62 ; CHECK: ret define void @test6(double %x, double* %y) { store double %x, double* %y, align 8 @@ -50,7 +50,7 @@ define void @test6(double %x, double* %y) { } ; CHECK-LABEL: @test7 -; CHECK: vmovssz (%rdi), %xmm0 +; CHECK: vmovss (%rdi), %xmm0 ## encoding: [0x62 ; CHECK: ret define float @test7(i32* %x) { %y = load i32* %x @@ -59,7 +59,7 @@ define float @test7(i32* %x) { } ; CHECK-LABEL: @test8 -; CHECK: vmovdz %xmm0, %eax +; CHECK: vmovd %xmm0, %eax ## encoding: [0x62 ; CHECK: ret define i32 @test8(<4 x i32> %x) { %res = extractelement <4 x i32> %x, i32 0 @@ -67,7 +67,7 @@ define i32 @test8(<4 x i32> %x) { } ; CHECK-LABEL: @test9 -; CHECK: vmovqz %xmm0, %rax +; CHECK: vmovq %xmm0, %rax ## encoding: [0x62 ; CHECK: ret define i64 @test9(<2 x i64> %x) { %res = extractelement <2 x i64> %x, i32 0 @@ -75,7 +75,7 @@ define i64 @test9(<2 x i64> %x) { } ; CHECK-LABEL: @test10 -; CHECK: vmovdz (%rdi) +; CHECK: vmovd (%rdi), %xmm0 ## encoding: [0x62 ; CHECK: ret define <4 x i32> @test10(i32* %x) { %y = load i32* %x, align 4 @@ -84,7 +84,7 @@ define <4 x i32> @test10(i32* %x) { } ; CHECK-LABEL: @test11 -; CHECK: vmovssz (%rdi) +; CHECK: vmovss (%rdi), %xmm0 ## encoding: [0x62 ; CHECK: ret define <4 x float> @test11(float* %x) { %y = load float* %x, align 4 @@ -93,7 +93,7 @@ define <4 x float> @test11(float* %x) { } ; CHECK-LABEL: @test12 -; CHECK: vmovsdz (%rdi) +; CHECK: vmovsd (%rdi), %xmm0 ## encoding: [0x62 ; CHECK: ret define <2 x double> @test12(double* %x) { %y = load double* %x, align 8 @@ -102,7 +102,7 @@ define <2 x double> @test12(double* %x) { } ; CHECK-LABEL: @test13 -; CHECK: vmovqz %rdi +; CHECK: vmovq %rdi, %xmm0 ## encoding: [0x62 ; CHECK: ret define <2 x i64> @test13(i64 %x) { %res = insertelement <2 x i64>zeroinitializer, i64 %x, i32 0 @@ -110,7 +110,7 @@ define <2 x i64> @test13(i64 %x) { } ; CHECK-LABEL: @test14 -; CHECK: vmovdz %edi +; CHECK: vmovd %edi, %xmm0 ## encoding: [0x62 ; CHECK: ret define <4 x i32> @test14(i32 %x) { %res = insertelement <4 x i32>zeroinitializer, i32 %x, i32 0 @@ -118,7 +118,7 @@ define <4 x i32> @test14(i32 %x) { } ; CHECK-LABEL: @test15 -; CHECK: vmovdz (%rdi) +; CHECK: vmovd (%rdi), %xmm0 ## encoding: [0x62 ; CHECK: ret define <4 x i32> @test15(i32* %x) { %y = load i32* %x, align 4 diff --git a/test/CodeGen/X86/avx512-shuffle.ll b/test/CodeGen/X86/avx512-shuffle.ll index e32d62453d..84a87e23f3 100644 --- a/test/CodeGen/X86/avx512-shuffle.ll +++ b/test/CodeGen/X86/avx512-shuffle.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s ; CHECK: LCP ; CHECK: .long 2 ; CHECK: .long 5 @@ -107,7 +107,7 @@ define <16 x i32> @test11(<16 x i32> %a, <16 x i32>* %b) nounwind { } ; CHECK-LABEL: test12 -; CHECK: vmovlhpsz %xmm +; CHECK: vmovlhps {{.*}}## encoding: [0x62 ; CHECK: ret define <4 x i32> @test12(<4 x i32> %a, <4 x i32> %b) nounwind { %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5> @@ -186,7 +186,7 @@ define <16 x float> @test21(<16 x float> %a, <16 x float> %c) { } ; CHECK-LABEL: test22 -; CHECK: vmovhlpsz %xmm +; CHECK: vmovhlps {{.*}}## encoding: [0x62 ; CHECK: ret define <4 x i32> @test22(<4 x i32> %a, <4 x i32> %b) nounwind { %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 6, i32 7> diff --git a/test/CodeGen/X86/avx512-vbroadcast-crash.ll b/test/CodeGen/X86/avx512-vbroadcast-crash.ll deleted file mode 100644 index ed617f5360..0000000000 --- a/test/CodeGen/X86/avx512-vbroadcast-crash.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s - -define <16 x i32> @test_vbroadcast() { - ; CHECK: vpbroadcastd -entry: - %0 = sext <16 x i1> zeroinitializer to <16 x i32> - %1 = fcmp uno <16 x float> undef, zeroinitializer - %2 = sext <16 x i1> %1 to <16 x i32> - %3 = select <16 x i1> %1, <16 x i32> %0, <16 x i32> %2 - ret <16 x i32> %3 -} diff --git a/test/CodeGen/X86/avx512-vbroadcast.ll b/test/CodeGen/X86/avx512-vbroadcast.ll index 6f89d6ce23..9c6db11d8f 100644 --- a/test/CodeGen/X86/avx512-vbroadcast.ll +++ b/test/CodeGen/X86/avx512-vbroadcast.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s ;CHECK-LABEL: _inreg16xi32: ;CHECK: vpbroadcastd {{.*}}, %zmm @@ -19,7 +19,7 @@ define <8 x i64> @_inreg8xi64(i64 %a) { } ;CHECK-LABEL: _inreg16xfloat: -;CHECK: vbroadcastssz {{.*}}, %zmm +;CHECK: vbroadcastss {{.*}}, %zmm ;CHECK: ret define <16 x float> @_inreg16xfloat(float %a) { %b = insertelement <16 x float> undef, float %a, i32 0 @@ -28,7 +28,7 @@ define <16 x float> @_inreg16xfloat(float %a) { } ;CHECK-LABEL: _inreg8xdouble: -;CHECK: vbroadcastsdz {{.*}}, %zmm +;CHECK: vbroadcastsd {{.*}}, %zmm ;CHECK: ret define <8 x double> @_inreg8xdouble(double %a) { %b = insertelement <8 x double> undef, double %a, i32 0 @@ -45,9 +45,20 @@ define <16 x i32> @_xmm16xi32(<16 x i32> %a) { } ;CHECK-LABEL: _xmm16xfloat -;CHECK: vbroadcastssz +;CHECK: vbroadcastss {{.*}}## encoding: [0x62 ;CHECK: ret define <16 x float> @_xmm16xfloat(<16 x float> %a) { %b = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> zeroinitializer ret <16 x float> %b } + +define <16 x i32> @test_vbroadcast() { + ; CHECK: vpbroadcastd +entry: + %0 = sext <16 x i1> zeroinitializer to <16 x i32> + %1 = fcmp uno <16 x float> undef, zeroinitializer + %2 = sext <16 x i1> %1 to <16 x i32> + %3 = select <16 x i1> %1, <16 x i32> %0, <16 x i32> %2 + ret <16 x i32> %3 +} + |