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author | Preston Gurd <preston.gurd@intel.com> | 2012-03-19 14:10:12 +0000 |
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committer | Preston Gurd <preston.gurd@intel.com> | 2012-03-19 14:10:12 +0000 |
commit | 3e99b715d1f9fd3db9ee3847d845e2804bd82280 (patch) | |
tree | 0b54ed3d5687b608f766bb41b9a3cc507e518027 /test | |
parent | 8118c94a55b7e3d6bcd43b4a043c922d8e20a8aa (diff) | |
download | llvm-3e99b715d1f9fd3db9ee3847d845e2804bd82280.tar.gz llvm-3e99b715d1f9fd3db9ee3847d845e2804bd82280.tar.bz2 llvm-3e99b715d1f9fd3db9ee3847d845e2804bd82280.tar.xz |
This patch adds X86 instruction itineraries for non-pseudo opcodes in
X86InstrCompiler.td.
It also adds –mcpu-generic to the legalize-shift-64.ll test so the test
will pass if run on an Intel Atom CPU, which would otherwise
produce an instruction schedule which differs from that which the test expects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153033 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/X86/legalize-shift-64.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/X86/legalize-shift-64.ll b/test/CodeGen/X86/legalize-shift-64.ll index 2026472692..c9f2fc27db 100644 --- a/test/CodeGen/X86/legalize-shift-64.ll +++ b/test/CodeGen/X86/legalize-shift-64.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=x86 < %s | FileCheck %s +; RUN: llc -mcpu=generic -march=x86 < %s | FileCheck %s define i64 @test1(i32 %xx, i32 %test) nounwind { %conv = zext i32 %xx to i64 |