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authorJack Carter <jack.carter@imgtec.com>2013-09-25 23:50:44 +0000
committerJack Carter <jack.carter@imgtec.com>2013-09-25 23:50:44 +0000
commit42d9ca629934d0c20ac19949399ce4faa9a7bbb3 (patch)
treeaf44743f99083c0ccf579047e07e2f541f3ba1a2 /test
parent825e5583b6c3161bb02074dc48cd07dafdf9545c (diff)
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[mips][msa] Direct Object Emission support for the MSA instruction set.
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191412 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/MC/Mips/msa/test_2rf.s12
1 files changed, 12 insertions, 0 deletions
diff --git a/test/MC/Mips/msa/test_2rf.s b/test/MC/Mips/msa/test_2rf.s
new file mode 100644
index 0000000000..7f80db7cae
--- /dev/null
+++ b/test/MC/Mips/msa/test_2rf.s
@@ -0,0 +1,12 @@
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 -mattr=+msa -arch=mips | FileCheck %s
+#
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa -arch=mips -filetype=obj -o - | llvm-objdump -d -triple=mipsel-unknown-linux -mattr=+msa -arch=mips - | FileCheck %s -check-prefix=CHECKOBJDUMP
+#
+# CHECK: fclass.w $w26, $w12 # encoding: [0x7b,0x20,0x66,0x9e]
+# CHECK: fclass.d $w24, $w17 # encoding: [0x7b,0x21,0x8e,0x1e]
+
+# CHECKOBJDUMP: fclass.w $w26, $w12
+# CHECKOBJDUMP: fclass.d $w24, $w17
+
+ fclass.w $w26, $w12
+ fclass.d $w24, $w17