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authorBob Wilson <bob.wilson@apple.com>2010-12-13 23:02:37 +0000
committerBob Wilson <bob.wilson@apple.com>2010-12-13 23:02:37 +0000
commit4711d5cda37fc4a756f83fc1090e85ec9302c52f (patch)
tree99f985c78022ed2096100e554e66f39e1d104ad1 /test
parent0e6d540d1745ea00042ca6d56d6e5929e7c8e5ca (diff)
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Remove the rest of the *_sfp Neon instruction patterns.
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions. This change made a big difference in the code generated for the CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing a fine job, but some instructions that were previously moved outside the loop are not moved now. It's using fewer VFP registers now, which is generally a good thing, so I think the estimates for register pressure changed and that affected the LICM behavior. Since that isn't obviously wrong, I've just changed the test file. This completes the work for Radar 8711675. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121730 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/Thumb2/cross-rc-coalescing-2.ll5
1 files changed, 0 insertions, 5 deletions
diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
index c169fb334a..b8c8cb122a 100644
--- a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
+++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
@@ -15,9 +15,6 @@ bb.nph: ; preds = %bb5
; Loop preheader
; CHECK: vmov.f32
-; CHECK: vsub.f32
-; CHECK: vadd.f32
-; CHECK: vmul.f32
bb7: ; preds = %bb9, %bb.nph
%s1.02 = phi float [ undef, %bb.nph ], [ %35, %bb9 ] ; <float> [#uses=3]
%tmp79 = add i32 undef, undef ; <i32> [#uses=1]
@@ -73,8 +70,6 @@ bb8: ; preds = %bb8, %bb7
br i1 %34, label %bb8, label %bb9
bb9: ; preds = %bb8
-; CHECK: %bb9
-; CHECK: vmov.f32
%35 = fadd float 0.000000e+00, undef ; <float> [#uses=1]
br label %bb7
}