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| author | Kevin Qin <Kevin.Qin@arm.com> | 2013-12-24 08:16:06 +0000 |
|---|---|---|
| committer | Kevin Qin <Kevin.Qin@arm.com> | 2013-12-24 08:16:06 +0000 |
| commit | 4905226c1c0a1324f4df38acee0ed6bc891ed2d1 (patch) | |
| tree | c0e9c2105ecc02bf6d7be917cbd5e0954de11232 /test | |
| parent | 0e8c1f5ca33f413cdd320fd1dcfebdba34b14f06 (diff) | |
| download | llvm-4905226c1c0a1324f4df38acee0ed6bc891ed2d1.tar.gz llvm-4905226c1c0a1324f4df38acee0ed6bc891ed2d1.tar.bz2 llvm-4905226c1c0a1324f4df38acee0ed6bc891ed2d1.tar.xz | |
[AArch64 NEON] Fix a bug when lowering BUILD_VECTOR.
DAG.getVectorShuffle() doesn't always return a vector_shuffle node.
If mask is the exact sequence of it's operand(For example, operand_0
is v8i8, and the mask is 0, 1, 2, 3, 4, 5, 6, 7), it will directly
return that operand. So a check is added here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197967 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/AArch64/neon-copy.ll | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/test/CodeGen/AArch64/neon-copy.ll b/test/CodeGen/AArch64/neon-copy.ll index c783c00c71..881a858bc1 100644 --- a/test/CodeGen/AArch64/neon-copy.ll +++ b/test/CodeGen/AArch64/neon-copy.ll @@ -703,4 +703,26 @@ define <4 x i32> @testDUP.v1i32(<1 x i32> %a) { %e = insertelement <4 x i32> %d, i32 %b, i32 2 %f = insertelement <4 x i32> %e, i32 %b, i32 3 ret <4 x i32> %f -}
\ No newline at end of file +} + +define <8 x i8> @getl(<16 x i8> %x) #0 { +; CHECK-LABEL: getl: +; CHECK: ret + %vecext = extractelement <16 x i8> %x, i32 0 + %vecinit = insertelement <8 x i8> undef, i8 %vecext, i32 0 + %vecext1 = extractelement <16 x i8> %x, i32 1 + %vecinit2 = insertelement <8 x i8> %vecinit, i8 %vecext1, i32 1 + %vecext3 = extractelement <16 x i8> %x, i32 2 + %vecinit4 = insertelement <8 x i8> %vecinit2, i8 %vecext3, i32 2 + %vecext5 = extractelement <16 x i8> %x, i32 3 + %vecinit6 = insertelement <8 x i8> %vecinit4, i8 %vecext5, i32 3 + %vecext7 = extractelement <16 x i8> %x, i32 4 + %vecinit8 = insertelement <8 x i8> %vecinit6, i8 %vecext7, i32 4 + %vecext9 = extractelement <16 x i8> %x, i32 5 + %vecinit10 = insertelement <8 x i8> %vecinit8, i8 %vecext9, i32 5 + %vecext11 = extractelement <16 x i8> %x, i32 6 + %vecinit12 = insertelement <8 x i8> %vecinit10, i8 %vecext11, i32 6 + %vecext13 = extractelement <16 x i8> %x, i32 7 + %vecinit14 = insertelement <8 x i8> %vecinit12, i8 %vecext13, i32 7 + ret <8 x i8> %vecinit14 +} |