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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-05-05 21:47:15 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-05-05 21:47:15 +0000 |
| commit | 4b84b524e5866a907939aae23711797153343598 (patch) | |
| tree | f975b8f560e8d804222c4ed37ec20514e2c6a65d /test | |
| parent | 33a4854fcb13a830a440aa16c8a9cdf7d1592dbb (diff) | |
| download | llvm-4b84b524e5866a907939aae23711797153343598.tar.gz llvm-4b84b524e5866a907939aae23711797153343598.tar.bz2 llvm-4b84b524e5866a907939aae23711797153343598.tar.xz | |
R600: Expand i64 ISD:SUB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208005 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/R600/sub.ll | 55 |
1 files changed, 37 insertions, 18 deletions
diff --git a/test/CodeGen/R600/sub.ll b/test/CodeGen/R600/sub.ll index 5fdd2b820c..e321ed67a6 100644 --- a/test/CodeGen/R600/sub.ll +++ b/test/CodeGen/R600/sub.ll @@ -1,13 +1,12 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s -;EG-CHECK: @test2 -;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;FUNC-LABEL: @test2 +;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: @test2 -;SI-CHECK: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -18,17 +17,16 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { ret void } -;EG-CHECK: @test4 -;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;FUNC-LABEL: @test4 +;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: @test4 -;SI-CHECK: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -38,3 +36,24 @@ define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void } + +;FUNC_LABEL: @test5 + +;EG-DAG: SETGE_UINT +;EG-DAG: CNDE_INT +;EG-DAG: SUB_INT +;EG-DAG: SUB_INT +;EG-DAG: SUB_INT + +;SI: S_XOR_B64 +;SI-DAG: S_ADD_I32 +;SI-DAG: S_ADDC_U32 +;SI-DAG: S_ADD_I32 +;SI-DAG: S_ADDC_U32 + +define void @test5(i64 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = sub i64 %a, %b + store i64 %0, i64 addrspace(1)* %out + ret void +} |