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author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-02-20 12:42:54 +0000 |
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committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-02-20 12:42:54 +0000 |
commit | 52981c4b6016d9f0e295e0771ec0a50dd073b4b3 (patch) | |
tree | ccb38cb2e26c468e41f6c039be8acb00bd60b19b /test | |
parent | 1479c9bb392325688b72e5829bbb7939c4a079a4 (diff) | |
download | llvm-52981c4b6016d9f0e295e0771ec0a50dd073b4b3.tar.gz llvm-52981c4b6016d9f0e295e0771ec0a50dd073b4b3.tar.bz2 llvm-52981c4b6016d9f0e295e0771ec0a50dd073b4b3.tar.xz |
I optimized the following patterns:
sext <4 x i1> to <4 x i64>
sext <4 x i8> to <4 x i64>
sext <4 x i16> to <4 x i64>
I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns:
(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
The sext_in_reg (v4i32 x) may be lowered to shl+sar operations.
The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution.
I also added a cost of this operations to the AVX costs table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175619 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/Analysis/CostModel/X86/cast.ll | 12 | ||||
-rwxr-xr-x | test/CodeGen/X86/avx-sext.ll | 23 |
2 files changed, 34 insertions, 1 deletions
diff --git a/test/Analysis/CostModel/X86/cast.ll b/test/Analysis/CostModel/X86/cast.ll index cedc682598..bacc778691 100644 --- a/test/Analysis/CostModel/X86/cast.ll +++ b/test/Analysis/CostModel/X86/cast.ll @@ -44,6 +44,10 @@ define i32 @zext_sext(<8 x i1> %in) { %B = zext <8 x i16> undef to <8 x i32> ;CHECK: cost of 1 {{.*}} sext %C = sext <4 x i32> undef to <4 x i64> + ;CHECK: cost of 8 {{.*}} sext + %C1 = sext <4 x i8> undef to <4 x i64> + ;CHECK: cost of 8 {{.*}} sext + %C2 = sext <4 x i16> undef to <4 x i64> ;CHECK: cost of 1 {{.*}} zext %D = zext <4 x i32> undef to <4 x i64> @@ -59,7 +63,7 @@ define i32 @zext_sext(<8 x i1> %in) { ret i32 undef } -define i32 @masks(<8 x i1> %in) { +define i32 @masks8(<8 x i1> %in) { ;CHECK: cost of 6 {{.*}} zext %Z = zext <8 x i1> %in to <8 x i32> ;CHECK: cost of 9 {{.*}} sext @@ -67,3 +71,9 @@ define i32 @masks(<8 x i1> %in) { ret i32 undef } +define i32 @masks4(<4 x i1> %in) { + ;CHECK: cost of 8 {{.*}} sext + %S = sext <4 x i1> %in to <4 x i64> + ret i32 undef +} + diff --git a/test/CodeGen/X86/avx-sext.ll b/test/CodeGen/X86/avx-sext.ll index 8d7d79db7d..7ae0d36c08 100755 --- a/test/CodeGen/X86/avx-sext.ll +++ b/test/CodeGen/X86/avx-sext.ll @@ -142,3 +142,26 @@ define <8 x i16> @load_sext_test6(<8 x i8> *%ptr) { %Y = sext <8 x i8> %X to <8 x i16> ret <8 x i16>%Y } + +; AVX: sext_4i1_to_4i64 +; AVX: vpslld $31 +; AVX: vpsrad $31 +; AVX: vpmovsxdq +; AVX: vpmovsxdq +; AVX: ret +define <4 x i64> @sext_4i1_to_4i64(<4 x i1> %mask) { + %extmask = sext <4 x i1> %mask to <4 x i64> + ret <4 x i64> %extmask +} + +; AVX: sext_4i8_to_4i64 +; AVX: vpslld $24 +; AVX: vpsrad $24 +; AVX: vpmovsxdq +; AVX: vpmovsxdq +; AVX: ret +define <4 x i64> @sext_4i8_to_4i64(<4 x i8> %mask) { + %extmask = sext <4 x i8> %mask to <4 x i64> + ret <4 x i64> %extmask +} + |