diff options
| author | Kevin Enderby <enderby@apple.com> | 2010-12-15 01:24:36 +0000 |
|---|---|---|
| committer | Kevin Enderby <enderby@apple.com> | 2010-12-15 01:24:36 +0000 |
| commit | 53ef11884ff273715f1924ea13853ec18510dae1 (patch) | |
| tree | 205292eedf838914ece600622c4d5ec27ecd1d2c /test | |
| parent | 24d7fa2b6ed7956c4d3c5d778c2dd7dac1165e36 (diff) | |
| download | llvm-53ef11884ff273715f1924ea13853ec18510dae1.tar.gz llvm-53ef11884ff273715f1924ea13853ec18510dae1.tar.bz2 llvm-53ef11884ff273715f1924ea13853ec18510dae1.tar.xz | |
Add some more MC tests for ARM arithmetic instructions that update or don't
update the condition codes. These come from my test generator and are just
the ones that MC currently assembles correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121830 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/arm_instructions.s | 67 |
1 files changed, 59 insertions, 8 deletions
diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s index 3aafe05b5c..fe59dc835e 100644 --- a/test/MC/ARM/arm_instructions.s +++ b/test/MC/ARM/arm_instructions.s @@ -56,11 +56,62 @@ stmda r2!, {r1,r3-r6,sp} stmdb r2!, {r1,r3-r6,sp} -@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0] - and r1, r2, r3 -@ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0] - ands r1, r2, r3 -@ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0] - eor r1, r2, r3 -@ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0] - eors r1, r2, r3 +@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0] + and r1,r2,r3 + +@ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0] + ands r1,r2,r3 + +@ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0] + eor r1,r2,r3 + +@ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0] + eors r1,r2,r3 + +@ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0] + sub r1,r2,r3 + +@ CHECK: subs r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0] + subs r1,r2,r3 + +@ CHECK: add r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0] + add r1,r2,r3 + +@ CHECK: adds r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0] + adds r1,r2,r3 + +@ CHECK: adc r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0] + adc r1,r2,r3 + +@ CHECK: sbc r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe0] + sbc r1,r2,r3 + +@ CHECK: orr r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1] + orr r1,r2,r3 + +@ CHECK: orrs r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe1] + orrs r1,r2,r3 + +@ CHECK: bic r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1] + bic r1,r2,r3 + +@ CHECK: bics r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1] + bics r1,r2,r3 + +@ CHECK: mov r1, r2 @ encoding: [0x02,0x10,0xa0,0xe1] + mov r1,r2 + +@ CHECK: mvn r1, r2 @ encoding: [0x02,0x10,0xe0,0xe1] + mvn r1,r2 + +@ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1] + mvns r1,r2 + +@ CHECK: rsb r1, r2, r3 @ encoding: [0x03,0x10,0x62,0xe0] + rsb r1,r2,r3 + +@ CHECK: rsc r1, r2, r3 @ encoding: [0x03,0x10,0xe2,0xe0] + rsc r1,r2,r3 + +@ CHECK: mlas r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0xe0] + mlas r1,r2,r3,r4 |