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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-04-04 22:16:36 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-04-04 22:16:36 +0000 |
commit | 56ce6b35209723cc453a6258a44f442d63be2b64 (patch) | |
tree | b5401c3397d32d95f04753e06d32f6401c7632d9 /test | |
parent | 657a4e774ca27ec3b74100b893bdc08654bc916a (diff) | |
download | llvm-56ce6b35209723cc453a6258a44f442d63be2b64.tar.gz llvm-56ce6b35209723cc453a6258a44f442d63be2b64.tar.bz2 llvm-56ce6b35209723cc453a6258a44f442d63be2b64.tar.xz |
Reapply 154038 without the failing test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154062 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/Mips/mips64fpldst.ll | 8 | ||||
-rw-r--r-- | test/CodeGen/Mips/mips64intldst.ll | 22 |
2 files changed, 15 insertions, 15 deletions
diff --git a/test/CodeGen/Mips/mips64fpldst.ll b/test/CodeGen/Mips/mips64fpldst.ll index abeff095c4..24647b20bf 100644 --- a/test/CodeGen/Mips/mips64fpldst.ll +++ b/test/CodeGen/Mips/mips64fpldst.ll @@ -12,7 +12,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0) ; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: funcfl1 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(f0) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0) ; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]]) %0 = load float* @f0, align 4 ret float %0 @@ -24,7 +24,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0) ; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: funcfl2 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(d0) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0) ; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]]) %0 = load double* @d0, align 8 ret double %0 @@ -36,7 +36,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0) ; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: funcfs1 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(f0) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0) ; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]]) %0 = load float* @f1, align 4 store float %0, float* @f0, align 4 @@ -49,7 +49,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0) ; CHECK-N64: sdc1 $f{{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: funcfs2 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(d0) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0) ; CHECK-N32: sdc1 $f{{[0-9]+}}, 0($[[R0]]) %0 = load double* @d1, align 8 store double %0, double* @d0, align 8 diff --git a/test/CodeGen/Mips/mips64intldst.ll b/test/CodeGen/Mips/mips64intldst.ll index af3a2f80de..0e310a8670 100644 --- a/test/CodeGen/Mips/mips64intldst.ll +++ b/test/CodeGen/Mips/mips64intldst.ll @@ -16,7 +16,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(c) ; CHECK-N64: lb ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: func1 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(c) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(c) ; CHECK-N32: lb ${{[0-9]+}}, 0($[[R0]]) %0 = load i8* @c, align 4 %conv = sext i8 %0 to i64 @@ -29,7 +29,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(s) ; CHECK-N64: lh ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: func2 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(s) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(s) ; CHECK-N32: lh ${{[0-9]+}}, 0($[[R0]]) %0 = load i16* @s, align 4 %conv = sext i16 %0 to i64 @@ -42,7 +42,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(i) ; CHECK-N64: lw ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: func3 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(i) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(i) ; CHECK-N32: lw ${{[0-9]+}}, 0($[[R0]]) %0 = load i32* @i, align 4 %conv = sext i32 %0 to i64 @@ -55,7 +55,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(l) ; CHECK-N64: ld ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: func4 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(l) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(l) ; CHECK-N32: ld ${{[0-9]+}}, 0($[[R0]]) %0 = load i64* @l, align 8 ret i64 %0 @@ -67,7 +67,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(uc) ; CHECK-N64: lbu ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: ufunc1 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(uc) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(uc) ; CHECK-N32: lbu ${{[0-9]+}}, 0($[[R0]]) %0 = load i8* @uc, align 4 %conv = zext i8 %0 to i64 @@ -80,7 +80,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(us) ; CHECK-N64: lhu ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: ufunc2 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(us) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(us) ; CHECK-N32: lhu ${{[0-9]+}}, 0($[[R0]]) %0 = load i16* @us, align 4 %conv = zext i16 %0 to i64 @@ -93,7 +93,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(ui) ; CHECK-N64: lwu ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: ufunc3 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(ui) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(ui) ; CHECK-N32: lwu ${{[0-9]+}}, 0($[[R0]]) %0 = load i32* @ui, align 4 %conv = zext i32 %0 to i64 @@ -106,7 +106,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(c) ; CHECK-N64: sb ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: sfunc1 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(c) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(c) ; CHECK-N32: sb ${{[0-9]+}}, 0($[[R0]]) %0 = load i64* @l1, align 8 %conv = trunc i64 %0 to i8 @@ -120,7 +120,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(s) ; CHECK-N64: sh ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: sfunc2 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(s) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(s) ; CHECK-N32: sh ${{[0-9]+}}, 0($[[R0]]) %0 = load i64* @l1, align 8 %conv = trunc i64 %0 to i16 @@ -134,7 +134,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(i) ; CHECK-N64: sw ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: sfunc3 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(i) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(i) ; CHECK-N32: sw ${{[0-9]+}}, 0($[[R0]]) %0 = load i64* @l1, align 8 %conv = trunc i64 %0 to i32 @@ -148,7 +148,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(l) ; CHECK-N64: sd ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: sfunc4 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(l) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(l) ; CHECK-N32: sd ${{[0-9]+}}, 0($[[R0]]) %0 = load i64* @l1, align 8 store i64 %0, i64* @l, align 8 |