Add assembly parsing support for "msr" and also fix its encoding. Also add

testcases for the disassembler to make sure it still works for "msr".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 67 insertions, 0 deletions

diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s
index 291a76131c..fbec7891c8 100644
--- a/test/MC/ARM/arm_instructions.s
+++ b/test/MC/ARM/arm_instructions.s
@@ -246,3 +246,39 @@
 @ CHECK: cpsie  if, #10 @ encoding: [0xca,0x00,0x0a,0xf1]
         cpsie  if, #10
 
+@ CHECK: msr  cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
+        msr  apsr, r0
+
+@ CHECK: msr  cpsr_s, r0 @ encoding: [0x00,0xf0,0x24,0xe1]
+        msr  apsr_g, r0
+
+@ CHECK: msr  cpsr_f, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
+        msr  apsr_nzcvq, r0
+
+@ CHECK: msr  cpsr_fs, r0 @ encoding: [0x00,0xf0,0x2c,0xe1]
+        msr  apsr_nzcvqg, r0
+
+@ CHECK: msr  cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
+        msr  cpsr_fc, r0
+
+@ CHECK: msr  cpsr_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1]
+        msr  cpsr_c, r0
+
+@ CHECK: msr  cpsr_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1]
+        msr  cpsr_x, r0
+
+@ CHECK: msr  cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
+        msr  cpsr_fc, r0
+
+@ CHECK: msr  cpsr_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1]
+        msr  cpsr_fsx, r0
+
+@ CHECK: msr  spsr_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1]
+        msr  spsr_fc, r0
+
+@ CHECK: msr  spsr_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1]
+        msr  spsr_fsxc, r0
+
+@ CHECK: msr  cpsr_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1]
+        msr  cpsr_fsxc, r0
+
diff --git a/test/MC/ARM/thumb2.s b/test/MC/ARM/thumb2.s
index be4e555dc4..cd093119e5 100644
--- a/test/MC/ARM/thumb2.s
+++ b/test/MC/ARM/thumb2.s
@@ -259,3 +259,28 @@
 @ CHECK: cpsie.w  if, #10 @ encoding: [0xaf,0xf3,0x6a,0x85]
   cpsie.w  if, #10
 
+@ CHECK: msr  cpsr_fc, r0 @ encoding: [0x80,0xf3,0x00,0x89]
+  msr  apsr, r0
+@ CHECK: msr  cpsr_s, r0 @ encoding: [0x80,0xf3,0x00,0x84]
+  msr  apsr_g, r0
+@ CHECK: msr  cpsr_f, r0 @ encoding: [0x80,0xf3,0x00,0x88]
+  msr  apsr_nzcvq, r0
+@ CHECK: msr  cpsr_fs, r0 @ encoding: [0x80,0xf3,0x00,0x8c]
+  msr  apsr_nzcvqg, r0
+@ CHECK: msr  cpsr_fc, r0 @ encoding: [0x80,0xf3,0x00,0x89]
+  msr  cpsr_fc, r0
+@ CHECK: msr  cpsr_c, r0 @ encoding: [0x80,0xf3,0x00,0x81]
+  msr  cpsr_c, r0
+@ CHECK: msr  cpsr_x, r0 @ encoding: [0x80,0xf3,0x00,0x82]
+  msr  cpsr_x, r0
+@ CHECK: msr  cpsr_fc, r0 @ encoding: [0x80,0xf3,0x00,0x89]
+  msr  cpsr_fc, r0
+@ CHECK: msr  cpsr_fsx, r0 @ encoding: [0x80,0xf3,0x00,0x8e]
+  msr  cpsr_fsx, r0
+@ CHECK: msr  spsr_fc, r0 @ encoding: [0x90,0xf3,0x00,0x89]
+  msr  spsr_fc, r0
+@ CHECK: msr  spsr_fsxc, r0 @ encoding: [0x90,0xf3,0x00,0x8f]
+  msr  spsr_fsxc, r0
+@ CHECK: msr  cpsr_fsxc, r0 @ encoding: [0x80,0xf3,0x00,0x8f]
+  msr  cpsr_fsxc, r0
+
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index 26bd182d78..0f6aeb7052 100644
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -127,3 +127,6 @@
 
 # CHECK: cpsie if, #10
 0xca 0x00 0x0a 0xf1
+
+# CHECK: msr cpsr_fc, r0
+0x00 0xf0 0x29 0xe1
diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt
index 4e8bc9baa2..6dab1237a1 100644
--- a/test/MC/Disassembler/ARM/thumb-tests.txt
+++ b/test/MC/Disassembler/ARM/thumb-tests.txt
@@ -115,3 +115,6 @@
 
 # CHECK: cpsie aif
 0x67 0xb6
+
+# CHECK: msr cpsr_fc, r0
+0x80 0xf3 0x00 0x89