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author | Silviu Baranga <silviu.baranga@arm.com> | 2012-03-20 15:54:56 +0000 |
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committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-03-20 15:54:56 +0000 |
commit | 5c062ad92672f22e61a4b20a9954af3db3b72bd6 (patch) | |
tree | f65d4278663391396a3ae5ab55a3a4b7021200ed /test | |
parent | 8da7a4668f6f32e565d426b5cca93eea9278f482 (diff) | |
download | llvm-5c062ad92672f22e61a4b20a9954af3db3b72bd6.tar.gz llvm-5c062ad92672f22e61a4b20a9954af3db3b72bd6.tar.bz2 llvm-5c062ad92672f22e61a4b20a9954af3db3b72bd6.tar.xz |
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt (renamed from test/MC/Disassembler/ARM/invalid-LSL-regform.txt) | 4 | ||||
-rw-r--r-- | test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt (renamed from test/MC/Disassembler/ARM/invalid-RSC-arm.txt) | 4 | ||||
-rw-r--r-- | test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt (renamed from test/MC/Disassembler/ARM/invalid-SSAT-arm.txt) | 4 | ||||
-rw-r--r-- | test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt (renamed from test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt) | 4 | ||||
-rw-r--r-- | test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt (renamed from test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt) | 6 |
5 files changed, 17 insertions, 5 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt index 6a1f11faf2..f7d6bc6edc 100644 --- a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -8,4 +8,6 @@ # # A8.6.89 LSL (register) # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; + +# CHECK: warning: potentially undefined instruction encoding 0x12 0xf1 0xa0 0xe1 diff --git a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt index 096b909bc6..5b13610949 100644 --- a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -6,4 +6,6 @@ # | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| # ------------------------------------------------------------------------------------------------- # if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; + +# CHECK: warning: potentially undefined instruction encoding 0x5f 0xf8 0xe4 0x30 diff --git a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt index b236f8ef4d..874378ed02 100644 --- a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -8,4 +8,6 @@ # # A8.6.183 SSAT # if d == 15 || n == 15 then UNPREDICTABLE; + +# CHECK:warning: potentially undefined instruction encoding 0x1a 0xf4 0xa0 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt index d3998bdc09..fef6125d28 100644 --- a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -7,4 +7,6 @@ # ------------------------------------------------------------------------------------------------- # # if t == 15 then UNPREDICTABLE + +# CHECK: warning: potentially undefined instruction encoding 0x00 0xf0 0xcf 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt index fb3e71106c..4c4c9abed2 100644 --- a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -10,3 +10,7 @@ # # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; 0x9f 0x5f 0x66 0xe6 + +# CHECK: warning: potentially undefined +# CHECK: uqadd8 r5, r6, pc + |