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| author | David Peixotto <dpeixott@codeaurora.org> | 2014-01-27 21:39:04 +0000 |
|---|---|---|
| committer | David Peixotto <dpeixott@codeaurora.org> | 2014-01-27 21:39:04 +0000 |
| commit | 66742f023c75e43e507763c72907f6836970e42c (patch) | |
| tree | aa444018bc473238549829487bfca4cb6764e945 /test | |
| parent | eea2f89d5d5e00e4602b3bef7dbd3f951c0bcaaf (diff) | |
| download | llvm-66742f023c75e43e507763c72907f6836970e42c.tar.gz llvm-66742f023c75e43e507763c72907f6836970e42c.tar.bz2 llvm-66742f023c75e43e507763c72907f6836970e42c.tar.xz | |
Fix unsupported addressing mode assertion for pld
Summary:
This commit gives an address mode to the PLD instruction. We
were getting an assertion failure in the frame lowering code
because we had code that was doing a pld of a stack allocated
address. The frame lowering was checking the address mode and
then asserting because pld had none defined.
This commit fixes pld for arm mode. There was a previous fix for
thumb mode in a separate commit. The commit for thumb mode
added a test in a separate file because it would otherwise fail
for arm. This commit moves the thumb test back into the prefetch.ll
file and adds the corresponding arm test.
Differential Revision: http://llvm-reviews.chandlerc.com/D2622
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200248 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/prefetch-thumb.ll | 22 | ||||
| -rw-r--r-- | test/CodeGen/ARM/prefetch.ll | 18 |
2 files changed, 18 insertions, 22 deletions
diff --git a/test/CodeGen/ARM/prefetch-thumb.ll b/test/CodeGen/ARM/prefetch-thumb.ll deleted file mode 100644 index e6f6ae8d18..0000000000 --- a/test/CodeGen/ARM/prefetch-thumb.ll +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: llc < %s -march=thumb -mattr=+v7 | FileCheck %s -check-prefix=THUMB2 -; TODO: This test case will be merged back into prefetch.ll when ARM mode issue is solved. - -declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind - -define void @t6() { -entry: -;ARM: t6: -;ARM: pld [sp] -;ARM: pld [sp, #50] - -;THUMB2: t6: -;THUMB2: pld [sp] -;THUMB2: pld [sp, #50] - -%red = alloca [100 x i8], align 1 -%0 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 0 -%1 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 50 -call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1) -call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1) -ret void -} diff --git a/test/CodeGen/ARM/prefetch.ll b/test/CodeGen/ARM/prefetch.ll index 5badb31148..e6cc849380 100644 --- a/test/CodeGen/ARM/prefetch.ll +++ b/test/CodeGen/ARM/prefetch.ll @@ -75,3 +75,21 @@ entry: tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 0 ) ret void } + +define void @t6() { +entry: +;ARM-LABEL: t6: +;ARM: pld [sp] +;ARM: pld [sp, #50] + +;THUMB2-LABEL: t6: +;THUMB2: pld [sp] +;THUMB2: pld [sp, #50] + +%red = alloca [100 x i8], align 1 +%0 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 0 +%1 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 50 +call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1) +call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1) +ret void +} |