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| author | Manman Ren <mren@apple.com> | 2012-12-04 00:52:33 +0000 |
|---|---|---|
| committer | Manman Ren <mren@apple.com> | 2012-12-04 00:52:33 +0000 |
| commit | 69261a644298bff1497d46c8cd38d688670f307b (patch) | |
| tree | 6552a5e87e17643db2693dab9046f435099467aa /test | |
| parent | 46608c0f648af75dd7260c3d881ca17353bb5982 (diff) | |
| download | llvm-69261a644298bff1497d46c8cd38d688670f307b.tar.gz llvm-69261a644298bff1497d46c8cd38d688670f307b.tar.bz2 llvm-69261a644298bff1497d46c8cd38d688670f307b.tar.xz | |
Stack Alignment: when creating stack objects in MachineFrameInfo, make sure
the alignment is clamped to TargetFrameLowering.getStackAlignment if the target
does not support stack realignment or the option "realign-stack" is off.
This will cause miscompile if the address is treated as aligned and add is
replaced with or in DAGCombine.
Added a bool StackRealignable to TargetFrameLowering to check whether stack
realignment is implemented for the target. Also added a bool RealignOption
to MachineFrameInfo to check whether the option "realign-stack" is on.
rdar://12713765
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169197 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/alloc-no-stack-realign.ll | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/alloc-no-stack-realign.ll b/test/CodeGen/ARM/alloc-no-stack-realign.ll new file mode 100644 index 0000000000..273041dee3 --- /dev/null +++ b/test/CodeGen/ARM/alloc-no-stack-realign.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -mtriple=armv7-apple-ios -O0 -realign-stack=0 | FileCheck %s -check-prefix=NO-REALIGN +; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s + +; rdar://12713765 +; When realign-stack is set to false, make sure we are not creating stack +; objects that are assumed to be 64-byte aligned. +@T3_retval = common global <16 x float> zeroinitializer, align 16 + +define void @test(<16 x float>* noalias sret %agg.result) nounwind ssp { +entry: +; CHECK: test +; CHECK: bic sp, sp, #63 +; CHECK: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48 +; CHECK: vst1.64 +; CHECK: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32 +; CHECK: vst1.64 +; CHECK: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16 +; CHECK: vst1.64 +; CHECK: vst1.64 +; CHECK: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48 +; CHECK: vst1.64 +; CHECK: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32 +; CHECK: vst1.64 +; CHECK: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16 +; CHECK: vst1.64 +; CHECK: vst1.64 +; NO-REALIGN: test +; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48 +; NO-REALIGN: vst1.64 +; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32 +; NO-REALIGN: vst1.64 +; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16 +; NO-REALIGN: vst1.64 +; NO-REALIGN: vst1.64 +; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48 +; NO-REALIGN: vst1.64 +; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32 +; NO-REALIGN: vst1.64 +; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16 +; NO-REALIGN: vst1.64 +; NO-REALIGN: vst1.64 + %retval = alloca <16 x float>, align 16 + %0 = load <16 x float>* @T3_retval, align 16 + store <16 x float> %0, <16 x float>* %retval + %1 = load <16 x float>* %retval + store <16 x float> %1, <16 x float>* %agg.result, align 16 + ret void +} |