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| author | Bill Wendling <isanbard@gmail.com> | 2010-10-04 20:24:01 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2010-10-04 20:24:01 +0000 |
| commit | 6cf6c79e8281835898cd105a30efedd44b554000 (patch) | |
| tree | 371a460697778f20e7dfd82a3b557b429ec739c4 /test | |
| parent | 3f55c24df9527de345f6cc960944840a7a101c6a (diff) | |
| download | llvm-6cf6c79e8281835898cd105a30efedd44b554000.tar.gz llvm-6cf6c79e8281835898cd105a30efedd44b554000.tar.bz2 llvm-6cf6c79e8281835898cd105a30efedd44b554000.tar.xz | |
The pshufw instruction came about in MMX2 when SSE was introduced. Don't place
it in with the SSSE3 instructions.
Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115552 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/Assembler/AutoUpgradeMMXIntrinsics.ll | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/test/Assembler/AutoUpgradeMMXIntrinsics.ll b/test/Assembler/AutoUpgradeMMXIntrinsics.ll index 898582ed24..54120ff9dc 100644 --- a/test/Assembler/AutoUpgradeMMXIntrinsics.ll +++ b/test/Assembler/AutoUpgradeMMXIntrinsics.ll @@ -4,6 +4,7 @@ ; RUN: grep {llvm\\.x86\\.mmx} %t | not grep {\\\<2 x i32\\\>} ; RUN: grep {llvm\\.x86\\.mmx} %t | not grep {\\\<4 x i16\\\>} ; RUN: grep {llvm\\.x86\\.mmx} %t | not grep {\\\<8 x i8\\\>} +; RUN: grep {llvm\\.x86\\.sse\\.pshuf\\.w} %t | not grep i32 ; Addition declare <8 x i8> @llvm.x86.mmx.padd.b(<8 x i8>, <8 x i8>) nounwind readnone @@ -207,6 +208,7 @@ declare void @llvm.x86.mmx.movnt.dq(i32*, <1 x i64>) nounwind readnone declare <1 x i64> @llvm.x86.mmx.palignr.b(<1 x i64>, <1 x i64>, i8) nounwind readnone declare i32 @llvm.x86.mmx.pextr.w(<1 x i64>, i32) nounwind readnone declare <1 x i64> @llvm.x86.mmx.pinsr.w(<1 x i64>, i32, i32) nounwind readnone +declare <4 x i16> @llvm.x86.ssse3.pshuf.w(<4 x i16>, i32) nounwind readnone define void @misc(<8 x i8> %A, <8 x i8> %B, <4 x i16> %C, <4 x i16> %D, <2 x i32> %E, <2 x i32> %F, <1 x i64> %G, <1 x i64> %H, i32* %I, i8 %J, i16 %K, i32 %L) { @@ -216,5 +218,6 @@ define void @misc(<8 x i8> %A, <8 x i8> %B, <4 x i16> %C, <4 x i16> %D, %r2 = call <1 x i64> @llvm.x86.mmx.palignr.b(<1 x i64> %G, <1 x i64> %H, i8 %J) %r3 = call i32 @llvm.x86.mmx.pextr.w(<1 x i64> %G, i32 37) %r4 = call <1 x i64> @llvm.x86.mmx.pinsr.w(<1 x i64> %G, i32 37, i32 927) + %r5 = call <4 x i16> @llvm.x86.ssse3.pshuf.w(<4 x i16> %C, i32 37) ret void } |