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| author | Jim Grosbach <grosbach@apple.com> | 2011-12-05 22:21:28 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-12-05 22:21:28 +0000 |
| commit | 6e507c645d469f525a46c4280cc29bd3078bb9d0 (patch) | |
| tree | 86ec782c23e00dd5a7ca061375c8404e9f056350 /test | |
| parent | 927b9df4c678371d3fb1308be90e76ed44af72f8 (diff) | |
| download | llvm-6e507c645d469f525a46c4280cc29bd3078bb9d0.tar.gz llvm-6e507c645d469f525a46c4280cc29bd3078bb9d0.tar.bz2 llvm-6e507c645d469f525a46c4280cc29bd3078bb9d0.tar.xz | |
Update tests for r145860. Add a few new ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145861 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/basic-thumb2-instructions.s | 4 | ||||
| -rw-r--r-- | test/MC/ARM/mode-switch.s | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index 456339f000..205ca35a45 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -99,12 +99,16 @@ _func: adds r7, r3, r1, lsl #31 adds.w r0, r3, r6, lsr #25 add.w r4, r8, r1, ror #12 + add r10, r8 + add r10, r10, r8 @ CHECK: add.w r1, r2, r8 @ encoding: [0x02,0xeb,0x08,0x01] @ CHECK: add.w r5, r9, r2, asr #32 @ encoding: [0x09,0xeb,0x22,0x05] @ CHECK: adds.w r7, r3, r1, lsl #31 @ encoding: [0x13,0xeb,0xc1,0x77] @ CHECK: adds.w r0, r3, r6, lsr #25 @ encoding: [0x13,0xeb,0x56,0x60] @ CHECK: add.w r4, r8, r1, ror #12 @ encoding: [0x08,0xeb,0x31,0x34] +@ CHECK: add r10, r8 @ encoding: [0xc2,0x44] +@ CHECK: add r10, r8 @ encoding: [0xc2,0x44] @------------------------------------------------------------------------------ diff --git a/test/MC/ARM/mode-switch.s b/test/MC/ARM/mode-switch.s index 9d4995439e..99bd4b5310 100644 --- a/test/MC/ARM/mode-switch.s +++ b/test/MC/ARM/mode-switch.s @@ -4,7 +4,7 @@ .code 16 add.w r0, r0, r1 -@ CHECK: add.w r0, r0, r1 @ encoding: [0x00,0xeb,0x01,0x00] +@ CHECK: add r0, r1 @ encoding: [0x08,0x44] .code 32 add r0, r0, r1 |