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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-11-30 13:47:57 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-11-30 13:47:57 +0000 |
| commit | 6fdef5ecd770f62366b75f1d4c8e17caf2fe0bec (patch) | |
| tree | 608742f7fea0bd8be7c7dd72f679c378b8955f8a /test | |
| parent | c7ff23aa67a6eb29312222e273adf92d5dd78f98 (diff) | |
| download | llvm-6fdef5ecd770f62366b75f1d4c8e17caf2fe0bec.tar.gz llvm-6fdef5ecd770f62366b75f1d4c8e17caf2fe0bec.tar.bz2 llvm-6fdef5ecd770f62366b75f1d4c8e17caf2fe0bec.tar.xz | |
[mips][msa] MSA loads and stores have a 10-bit offset. Account for this when lowering FrameIndex.
This prevents the compiler from emitting invalid ld.[bhwd]'s and st.[bhwd]'s
when the stack frame is between 512 and 32,768 bytes in size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195973 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/Mips/msa/frameindex.ll | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/msa/frameindex.ll b/test/CodeGen/Mips/msa/frameindex.ll new file mode 100644 index 0000000000..3088e1ba98 --- /dev/null +++ b/test/CodeGen/Mips/msa/frameindex.ll @@ -0,0 +1,85 @@ +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32-AE -check-prefix=MIPS32-BE %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32-AE -check-prefix=MIPS32-LE %s + +define void @loadstore_v16i8_near() nounwind { + ; MIPS32-AE: loadstore_v16i8_near: + + %1 = alloca <16 x i8> + %2 = load volatile <16 x i8>* %1 + ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0($sp) + store volatile <16 x i8> %2, <16 x i8>* %1 + ; MIPS32-AE: st.b [[R1]], 0($sp) + + ret void + ; MIPS32-AE: .size loadstore_v16i8_near +} + +define void @loadstore_v16i8_just_under_simm10() nounwind { + ; MIPS32-AE: loadstore_v16i8_just_under_simm10: + + %1 = alloca <16 x i8> + %2 = alloca [496 x i8] ; Push the frame right up to 512 bytes + + %3 = load volatile <16 x i8>* %1 + ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 496($sp) + store volatile <16 x i8> %3, <16 x i8>* %1 + ; MIPS32-AE: st.b [[R1]], 496($sp) + + ret void + ; MIPS32-AE: .size loadstore_v16i8_just_under_simm10 +} + +define void @loadstore_v16i8_just_over_simm10() nounwind { + ; MIPS32-AE: loadstore_v16i8_just_over_simm10: + + %1 = alloca <16 x i8> + %2 = alloca [497 x i8] ; Push the frame just over 512 bytes + + %3 = load volatile <16 x i8>* %1 + ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 512 + ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) + store volatile <16 x i8> %3, <16 x i8>* %1 + ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 512 + ; MIPS32-AE: st.b [[R1]], 0([[BASE]]) + + ret void + ; MIPS32-AE: .size loadstore_v16i8_just_over_simm10 +} + +define void @loadstore_v16i8_just_under_simm16() nounwind { + ; MIPS32-AE: loadstore_v16i8_just_under_simm16: + + %1 = alloca <16 x i8> + %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes + + %3 = load volatile <16 x i8>* %1 + ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) + store volatile <16 x i8> %3, <16 x i8>* %1 + ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: st.b [[R1]], 0([[BASE]]) + + ret void + ; MIPS32-AE: .size loadstore_v16i8_just_under_simm16 +} + +define void @loadstore_v16i8_just_over_simm16() nounwind { + ; MIPS32-AE: loadstore_v16i8_just_over_simm16: + + %1 = alloca <16 x i8> + %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes + + %3 = load volatile <16 x i8>* %1 + ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) + store volatile <16 x i8> %3, <16 x i8>* %1 + ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: st.b [[R1]], 0([[BASE]]) + + ret void + ; MIPS32-AE: .size loadstore_v16i8_just_over_simm16 +} |